1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
82 cpuId = tc->readCpuId();
83#if FULL_SYSTEM
84 for (int i = 0; i < threadContexts.size(); ++i) {
85 ThreadContext *tc = threadContexts[i];
86
87 // initialize CPU, including PC
88 TheISA::initCPU(tc, cpuId);
89 }
90#endif
91 if (hasPhysMemPort) {
92 bool snoop = false;
93 AddrRangeList pmAddrList;
94 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
95 physMemAddr = *pmAddrList.begin();
96 }
97 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
98 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
99 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
100}
101
102bool
103AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
104{
105 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
106 return true;
107}

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232 schedule(tickEvent, nextCycle());
233 break;
234 }
235 }
236 if (_status != Running) {
237 _status = Idle;
238 }
239 assert(threadContexts.size() == 1);
240 cpuId = tc->readCpuId();
241 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
242 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
243 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
244}
245
246
247void
248AtomicSimpleCPU::activateContext(int thread_num, int delay)
249{
250 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
251

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