1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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171{
172}
173
174void
175AtomicSimpleCPU::serialize(ostream &os)
176{
177 SimObject::State so_state = SimObject::getState();
178 SERIALIZE_ENUM(so_state);
179 Status _status = status();
180 SERIALIZE_ENUM(_status);
181 BaseSimpleCPU::serialize(os);
182 nameOut(os, csprintf("%s.tickEvent", name()));
183 tickEvent.serialize(os);
184}
185
186void
187AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
188{
189 SimObject::State so_state;
190 UNSERIALIZE_ENUM(so_state);
191 UNSERIALIZE_ENUM(_status);
192 BaseSimpleCPU::unserialize(cp, section);
193 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
194}
195
196void
197AtomicSimpleCPU::resume()
198{
199 if (_status == Idle || _status == SwitchedOut)

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208 tickEvent.schedule(nextCycle());
209 }
210 }
211}
212
213void
214AtomicSimpleCPU::switchOut()
215{
216 assert(status() == Running || status() == Idle);
217 _status = SwitchedOut;
218
219 tickEvent.squash();
220}
221
222
223void
224AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)

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