1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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495 numCycles++;
496
497 if (!curStaticInst || !curStaticInst->isDelayedCommit())
498 checkForInterrupts();
499
500 Fault fault = setupFetchRequest(ifetch_req);
501
502 if (fault == NoFault) {
503 ifetch_pkt->reinitFromRequest();
504
505 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
506 // ifetch_req is initialized to read the instruction directly
507 // into the CPU object's inst field.
508
509 dcache_access = false; // assume no dcache access
510 preExecute();
511
512 fault = curStaticInst->execute(this, traceData);
513 postExecute();
514
515 // @todo remove me after debugging with legion done
516 if (curStaticInst && (!curStaticInst->isMicroOp() ||
517 curStaticInst->isFirstMicroOp()))
518 instCnt++;
519
520 if (simulate_stalls) {
521 Tick icache_stall = icache_latency - cycles(1);
522 Tick dcache_stall =
523 dcache_access ? dcache_latency - cycles(1) : 0;
524 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
525 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
526 latency += cycles(stall_cycles+1);
527 else
528 latency += cycles(stall_cycles);
529 }
530
531 }
532
533 advancePC(fault);
534 }
535
536 if (_status != Idle)
537 tickEvent.schedule(curTick + latency);
538}
539
540
541////////////////////////////////////////////////////////////////////////

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