1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/atomic.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "sim/builder.hh"
39#include "sim/system.hh"
40
41using namespace std;

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146 data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
147 Packet::Broadcast);
148 data_read_pkt->dataStatic(&dataReg);
149
150 data_write_req = new Request();
151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
152 data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
153 Packet::Broadcast);
154}
155
156
157AtomicSimpleCPU::~AtomicSimpleCPU()
158{
159}
160
161void

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313
314 return fault;
315}
316
317#ifndef DOXYGEN_SHOULD_SKIP_THIS
318
319template
320Fault
321AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
322
323template
324Fault
325AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
326
327template
328Fault

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358
359
360template <class T>
361Fault
362AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
363{
364 // use the CPU's statically allocated write request and packet objects
365 Request *req = data_write_req;
366 PacketPtr pkt = data_write_pkt;
367
368 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
369
370 if (traceData) {
371 traceData->setAddr(addr);
372 }
373
374 // translate to physical address
375 Fault fault = thread->translateDataWriteReq(req);
376
377 // Now do the access.
378 if (fault == NoFault) {
379 bool do_access = true; // flag to suppress cache access
380
381 if (req->isLocked()) {
382 do_access = TheISA::handleLockedWrite(thread, req);
383 }
384
385 if (do_access) {
386 pkt->reinitFromRequest();
387 pkt->dataStatic(&data);
388
389 if (req->isMmapedIpr()) {
390 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
391 } else {
392 data = htog(data);
393 dcache_latency = dcachePort.sendAtomic(pkt);
394 }
395 dcache_access = true;
396
397#if !defined(NDEBUG)
398 if (pkt->result != Packet::Success)
399 panic("Unable to find responder for address pa = %#X va = %#X\n",
400 pkt->req->getPaddr(), pkt->req->getVaddr());
401#endif
402 }
403
404 if (res) {
405 *res = req->getScResult();
406 }
407 }
408
409 // This will need a new way to tell if it's hooked up to a cache or not.
410 if (req->isUncacheable())
411 recordEvent("Uncached Write");
412
413 // If the write needs to have a fault on the access, consider calling
414 // changeStatus() and changing it to "bad addr write" or something.

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