1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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72void
73AtomicSimpleCPU::init()
74{
75 BaseCPU::init();
76#if FULL_SYSTEM
77 for (int i = 0; i < threadContexts.size(); ++i) {
78 ThreadContext *tc = threadContexts[i];
79
80 // initialize the mem pointers
81 tc->init();
82
83 // initialize CPU, including PC
84 TheISA::initCPU(tc, tc->readCpuId());
85 }
86#endif
87}
88
89bool
90AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)

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235{
236 assert(thread_num == 0);
237 assert(thread);
238
239 assert(_status == Idle);
240 assert(!tickEvent.scheduled());
241
242 notIdleFraction++;
243 //Make sure ticks are still on multiples of cycles
244 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
245 _status = Running;
246}
247
248
249void
250AtomicSimpleCPU::suspendContext(int thread_num)

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