1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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115
116AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
117 : BaseSimpleCPU(p), tickEvent(this),
118 width(p->width), simulate_stalls(p->simulate_stalls),
119 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
120{
121 _status = Idle;
122
123 ifetch_req = new Request(true);
124 ifetch_req->setAsid(0);
125 // @todo fix me and get the real cpu iD!!!
126 ifetch_req->setCpuNum(0);
127 ifetch_req->setSize(sizeof(MachInst));
128 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
129 ifetch_pkt->dataStatic(&inst);
130
131 data_read_req = new Request(true);
132 // @todo fix me and get the real cpu iD!!!
133 data_read_req->setCpuNum(0);
134 data_read_req->setAsid(0);
135 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
136 Packet::Broadcast);
137 data_read_pkt->dataStatic(&dataReg);
138
139 data_write_req = new Request(true);
140 // @todo fix me and get the real cpu iD!!!
141 data_write_req->setCpuNum(0);
142 data_write_req->setAsid(0);
143 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
144 Packet::Broadcast);
145}
146
147
148AtomicSimpleCPU::~AtomicSimpleCPU()
149{
150}

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231 _status = Idle;
232}
233
234
235template <class T>
236Fault
237AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
238{
239 data_read_req->setVaddr(addr);
240 data_read_req->setSize(sizeof(T));
241 data_read_req->setFlags(flags);
242 data_read_req->setTime(curTick);
243
244 if (traceData) {
245 traceData->setAddr(addr);
246 }
247
248 // translate to physical address
249 Fault fault = cpuXC->translateDataReadReq(data_read_req);
250

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309 return read(addr, (uint32_t&)data, flags);
310}
311
312
313template <class T>
314Fault
315AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
316{
317 data_write_req->setVaddr(addr);
318 data_write_req->setTime(curTick);
319 data_write_req->setSize(sizeof(T));
320 data_write_req->setFlags(flags);
321
322 if (traceData) {
323 traceData->setAddr(addr);
324 }
325
326 // translate to physical address
327 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
328

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403{
404 Tick latency = cycles(1); // instruction takes one cycle by default
405
406 for (int i = 0; i < width; ++i) {
407 numCycles++;
408
409 checkForInterrupts();
410
411 ifetch_req->resetMin();
412 Fault fault = setupFetchRequest(ifetch_req);
413
414 if (fault == NoFault) {
415 ifetch_pkt->reinitFromRequest();
416
417 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
418 // ifetch_req is initialized to read the instruction directly
419 // into the CPU object's inst field.

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