1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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273 if (tickEvent.scheduled())
274 deschedule(tickEvent);
275
276 notIdleFraction = 0;
277 _status = Idle;
278}
279
280
281Fault
282AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
283 unsigned size, unsigned flags)
284{
285 // use the CPU's statically allocated read request and packet objects
286 Request *req = &data_read_req;
287
288 if (traceData) {

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397
398 // Now do the access.
399 if (fault == NoFault) {
400 MemCmd cmd = MemCmd::WriteReq; // default
401 bool do_access = true; // flag to suppress cache access
402
403 if (req->isLLSC()) {
404 cmd = MemCmd::StoreCondReq;
405 do_access = TheISA::handleLockedWrite(thread, req);
406 } else if (req->isSwap()) {
407 cmd = MemCmd::SwapReq;
408 if (req->isCondSwap()) {
409 assert(res);
410 req->setExtraData(*res);
411 }
412 }
413

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