1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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309 dataSize = secondAddr - addr;
310
311 dcache_latency = 0;
312
313 while(1) {
314 req->setVirt(0, addr, dataSize, flags, thread->readPC());
315
316 // translate to physical address
317 Fault fault = thread->dtb->translate(req, tc, false);
318
319 // Now do the access.
320 if (fault == NoFault) {
321 Packet pkt = Packet(req,
322 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
323 Packet::Broadcast);
324 pkt.dataStatic(dataPtr);
325

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365 dataPtr += dataSize;
366 //Adjust the size to get the remaining bytes.
367 dataSize = addr + sizeof(T) - secondAddr;
368 //And access the right address.
369 addr = secondAddr;
370 }
371}
372
373#ifndef DOXYGEN_SHOULD_SKIP_THIS
374
375template
376Fault
377AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
378
379template
380Fault

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447 dataSize = secondAddr - addr;
448
449 dcache_latency = 0;
450
451 while(1) {
452 req->setVirt(0, addr, dataSize, flags, thread->readPC());
453
454 // translate to physical address
455 Fault fault = thread->dtb->translate(req, tc, true);
456
457 // Now do the access.
458 if (fault == NoFault) {
459 MemCmd cmd = MemCmd::WriteReq; // default
460 bool do_access = true; // flag to suppress cache access
461
462 if (req->isLocked()) {
463 cmd = MemCmd::StoreCondReq;

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526 dataPtr += dataSize;
527 //Adjust the size to get the remaining bytes.
528 dataSize = addr + sizeof(T) - secondAddr;
529 //And access the right address.
530 addr = secondAddr;
531 }
532}
533
534
535#ifndef DOXYGEN_SHOULD_SKIP_THIS
536
537template
538Fault
539AtomicSimpleCPU::write(Twin32_t data, Addr addr,
540 unsigned flags, uint64_t *res);
541
542template

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