1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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708 Tick latency = ticks(1); // instruction takes one cycle by default
709
710 for (int i = 0; i < width; ++i) {
711 numCycles++;
712
713 if (!curStaticInst || !curStaticInst->isDelayedCommit())
714 checkForInterrupts();
715
716 checkPcEventQueue();
717
718 Fault fault = setupFetchRequest(&ifetch_req);
719
720 if (fault == NoFault) {
721 Tick icache_latency = 0;
722 bool icache_access = false;
723 dcache_access = false; // assume no dcache access
724
725 //Fetch more instruction memory if necessary

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