1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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495 numCycles++;
496
497 if (!curStaticInst || !curStaticInst->isDelayedCommit())
498 checkForInterrupts();
499
500 Fault fault = setupFetchRequest(ifetch_req);
501
502 if (fault == NoFault) {
503 Tick icache_latency = 0;
504 bool icache_access = false;
505 dcache_access = false; // assume no dcache access
506
507 //Fetch more instruction memory if necessary
508 if(predecoder.needMoreBytes())
509 {
510 icache_access = true;
511 ifetch_pkt->reinitFromRequest();
512
513 icache_latency = icachePort.sendAtomic(ifetch_pkt);
514 // ifetch_req is initialized to read the instruction directly
515 // into the CPU object's inst field.
516 }
517
518 preExecute();
519
520 if(curStaticInst)
521 {
522 fault = curStaticInst->execute(this, traceData);
523 postExecute();
524 }
525
526 // @todo remove me after debugging with legion done
527 if (curStaticInst && (!curStaticInst->isMicroOp() ||
528 curStaticInst->isFirstMicroOp()))
529 instCnt++;
530
531 if (simulate_stalls) {
532 Tick icache_stall =
533 icache_access ? icache_latency - cycles(1) : 0;
534 Tick dcache_stall =
535 dcache_access ? dcache_latency - cycles(1) : 0;
536 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
537 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
538 latency += cycles(stall_cycles+1);
539 else
540 latency += cycles(stall_cycles);
541 }
542
543 }
544 if(predecoder.needMoreBytes())
545 advancePC(fault);
546 }
547
548 if (_status != Idle)
549 tickEvent.schedule(curTick + latency);
550}
551
552
553////////////////////////////////////////////////////////////////////////

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