1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/builder.hh"
40#include "sim/system.hh"
41
42using namespace std;

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147 data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
148 Packet::Broadcast);
149 data_read_pkt->dataStatic(&dataReg);
150
151 data_write_req = new Request();
152 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
153 data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
154 Packet::Broadcast);
155 data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
156 Packet::Broadcast);
157}
158
159
160AtomicSimpleCPU::~AtomicSimpleCPU()
161{
162}
163
164void

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316
317 return fault;
318}
319
320#ifndef DOXYGEN_SHOULD_SKIP_THIS
321
322template
323Fault
324AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
325
326template
327Fault
328AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
329
330template
331Fault
332AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
333
334template
335Fault

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365
366
367template <class T>
368Fault
369AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
370{
371 // use the CPU's statically allocated write request and packet objects
372 Request *req = data_write_req;
373 PacketPtr pkt;
374
375 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
376
377 if (req->isSwap())
378 pkt = data_swap_pkt;
379 else
380 pkt = data_write_pkt;
381
382 if (traceData) {
383 traceData->setAddr(addr);
384 }
385
386 // translate to physical address
387 Fault fault = thread->translateDataWriteReq(req);
388
389 // Now do the access.
390 if (fault == NoFault) {
391 bool do_access = true; // flag to suppress cache access
392
393 if (req->isLocked()) {
394 do_access = TheISA::handleLockedWrite(thread, req);
395 }
396 if (req->isCondSwap()) {
397 assert(res);
398 req->setExtraData(*res);
399 }
400
401
402 if (do_access) {
403 pkt->reinitFromRequest();
404 pkt->dataStatic(&data);
405
406 if (req->isMmapedIpr()) {
407 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
408 } else {
409 data = htog(data);
410 dcache_latency = dcachePort.sendAtomic(pkt);
411 }
412 dcache_access = true;
413
414#if !defined(NDEBUG)
415 if (pkt->result != Packet::Success)
416 panic("Unable to find responder for address pa = %#X va = %#X\n",
417 pkt->req->getPaddr(), pkt->req->getVaddr());
418#endif
419 }
420
421 if (req->isSwap()) {
422 assert(res);
423 *res = pkt->get<T>();
424 }
425
426 if (req->isLocked()) {
427 uint64_t scResult = req->getExtraData();
428 if (scResult != 0) {
429 // clear failure counter
430 thread->setStCondFailures(0);
431 }
432 if (res) {
433 *res = req->getExtraData();
434 }
435 }
436 }
437
438 // This will need a new way to tell if it's hooked up to a cache or not.
439 if (req->isUncacheable())
440 recordEvent("Uncached Write");
441
442 // If the write needs to have a fault on the access, consider calling
443 // changeStatus() and changing it to "bad addr write" or something.

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