1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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248 _status = Idle;
249}
250
251
252template <class T>
253Fault
254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
255{
256 // use the CPU's statically allocated read request and packet objects
257 Request *req = data_read_req;
258 Packet *pkt = data_read_pkt;
259
260 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
261
262 if (traceData) {
263 traceData->setAddr(addr);
264 }
265
266 // translate to physical address
267 Fault fault = thread->translateDataReadReq(req);
268
269 // Now do the access.
270 if (fault == NoFault) {
271 pkt->reinitFromRequest();
272
273 dcache_latency = dcachePort.sendAtomic(pkt);
274 dcache_access = true;
275
276 assert(pkt->result == Packet::Success);
277 data = pkt->get();
278 }
279
280 // This will need a new way to tell if it has a dcache attached.
281 if (req->getFlags() & UNCACHEABLE)
282 recordEvent("Uncached Read");
283
284 return fault;
285}
286
287#ifndef DOXYGEN_SHOULD_SKIP_THIS
288
289template

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326 return read(addr, (uint32_t&)data, flags);
327}
328
329
330template <class T>
331Fault
332AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
333{
334 // use the CPU's statically allocated write request and packet objects
335 Request *req = data_write_req;
336 Packet *pkt = data_write_pkt;
337
338 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
339
340 if (traceData) {
341 traceData->setAddr(addr);
342 }
343
344 // translate to physical address
345 Fault fault = thread->translateDataWriteReq(req);
346
347 // Now do the access.
348 if (fault == NoFault) {
349 data = htog(data);
350 pkt->reinitFromRequest();
351 pkt->dataStatic(&data);
352
353 dcache_latency = dcachePort.sendAtomic(pkt);
354 dcache_access = true;
355
356 assert(pkt->result == Packet::Success);
357
358 if (res && req->getFlags() & LOCKED) {
359 *res = req->getScResult();
360 }
361 }
362
363 // This will need a new way to tell if it's hooked up to a cache or not.
364 if (req->getFlags() & UNCACHEABLE)
365 recordEvent("Uncached Write");
366
367 // If the write needs to have a fault on the access, consider calling
368 // changeStatus() and changing it to "bad addr write" or something.
369 return fault;
370}
371
372

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