| TimingSimpleCPU.py (6654:4c84e771cca7) | TimingSimpleCPU.py (7876:189b9b258779) |
|---|---|
| 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29from m5.params import * 30from BaseSimpleCPU import BaseSimpleCPU 31 32class TimingSimpleCPU(BaseSimpleCPU): 33 type = 'TimingSimpleCPU' 34 icache_port = Port("Instruction Port") 35 dcache_port = Port("Data Port") | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29from m5.params import * 30from BaseSimpleCPU import BaseSimpleCPU 31 32class TimingSimpleCPU(BaseSimpleCPU): 33 type = 'TimingSimpleCPU' 34 icache_port = Port("Instruction Port") 35 dcache_port = Port("Data Port") |
| 36 _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port'] | 36 _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port'] |