TimingSimpleCPU.py (5537:eaeed2bdf50d) TimingSimpleCPU.py (6654:4c84e771cca7)
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 13 unchanged lines hidden (view full) ---

22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Nathan Binkert
28
29from m5.params import *
30from m5 import build_env
31from BaseSimpleCPU import BaseSimpleCPU
32
33class TimingSimpleCPU(BaseSimpleCPU):
34 type = 'TimingSimpleCPU'
35 icache_port = Port("Instruction Port")
36 dcache_port = Port("Data Port")
37 _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
30from BaseSimpleCPU import BaseSimpleCPU
31
32class TimingSimpleCPU(BaseSimpleCPU):
33 type = 'TimingSimpleCPU'
34 icache_port = Port("Instruction Port")
35 dcache_port = Port("Data Port")
36 _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']