TimingSimpleCPU.py (4486:aaeb03a8a6e1) | TimingSimpleCPU.py (5236:0050ad4fb3ef) |
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1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33class TimingSimpleCPU(BaseCPU): 34 type = 'TimingSimpleCPU' 35 function_trace = Param.Bool(False, "Enable function trace") 36 function_trace_start = Param.Tick(0, "Cycle to start function trace") 37 if build_env['FULL_SYSTEM']: 38 profile = Param.Latency('0ns', "trace the kernel stack") 39 icache_port = Port("Instruction Port") 40 dcache_port = Port("Data Port") | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33class TimingSimpleCPU(BaseCPU): 34 type = 'TimingSimpleCPU' 35 function_trace = Param.Bool(False, "Enable function trace") 36 function_trace_start = Param.Tick(0, "Cycle to start function trace") 37 if build_env['FULL_SYSTEM']: 38 profile = Param.Latency('0ns', "trace the kernel stack") 39 icache_port = Port("Instruction Port") 40 dcache_port = Port("Data Port") |
41 _mem_ports = ['icache_port', 'dcache_port'] | 41 _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] |