1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29from m5.params import *
30from m5 import build_env
31from BaseSimpleCPU import BaseSimpleCPU
32
33class TimingSimpleCPU(BaseSimpleCPU):
34 type = 'TimingSimpleCPU'
35 function_trace = Param.Bool(False, "Enable function trace")
36 function_trace_start = Param.Tick(0, "Cycle to start function trace")
37 icache_port = Port("Instruction Port")
38 dcache_port = Port("Data Port")
39 _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']