| NonCachingSimpleCPU.py (13012:5fbc6b9c64bc) | NonCachingSimpleCPU.py (13665:9c7fe3811b88) |
|---|---|
| 1# Copyright (c) 2012, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from m5.params import * | 1# Copyright (c) 2012, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from m5.params import * |
| 39from AtomicSimpleCPU import AtomicSimpleCPU | 39from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU |
| 40 41class NonCachingSimpleCPU(AtomicSimpleCPU): 42 """Simple CPU model based on the atomic CPU. Unlike the atomic CPU, 43 this model causes the memory system to bypass caches and is 44 therefore slightly faster in some cases. However, its main purpose 45 is as a substitute for hardware virtualized CPUs when 46 stress-testing the memory system. 47 --- 13 unchanged lines hidden --- | 40 41class NonCachingSimpleCPU(AtomicSimpleCPU): 42 """Simple CPU model based on the atomic CPU. Unlike the atomic CPU, 43 this model causes the memory system to bypass caches and is 44 therefore slightly faster in some cases. However, its main purpose 45 is as a substitute for hardware virtualized CPUs when 46 stress-testing the memory system. 47 --- 13 unchanged lines hidden --- |