BaseSimpleCPU.py (10785:f56c10663a01) | BaseSimpleCPU.py (12563:8d59ed22ae79) |
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1# Copyright (c) 2008 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Gabe Black 28 | 1# Copyright (c) 2008 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Gabe Black 28 |
29from __future__ import print_function 30 |
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29from m5.defines import buildEnv 30from m5.params import * 31from BaseCPU import BaseCPU 32from DummyChecker import DummyChecker 33from BranchPredictor import * 34 35class BaseSimpleCPU(BaseCPU): 36 type = 'BaseSimpleCPU' 37 abstract = True 38 cxx_header = "cpu/simple/base.hh" 39 40 def addCheckerCpu(self): 41 if buildEnv['TARGET_ISA'] in ['arm']: 42 from ArmTLB import ArmTLB 43 44 self.checker = DummyChecker(workload = self.workload) 45 self.checker.itb = ArmTLB(size = self.itb.size) 46 self.checker.dtb = ArmTLB(size = self.dtb.size) 47 else: | 31from m5.defines import buildEnv 32from m5.params import * 33from BaseCPU import BaseCPU 34from DummyChecker import DummyChecker 35from BranchPredictor import * 36 37class BaseSimpleCPU(BaseCPU): 38 type = 'BaseSimpleCPU' 39 abstract = True 40 cxx_header = "cpu/simple/base.hh" 41 42 def addCheckerCpu(self): 43 if buildEnv['TARGET_ISA'] in ['arm']: 44 from ArmTLB import ArmTLB 45 46 self.checker = DummyChecker(workload = self.workload) 47 self.checker.itb = ArmTLB(size = self.itb.size) 48 self.checker.dtb = ArmTLB(size = self.dtb.size) 49 else: |
48 print "ERROR: Checker only supported under ARM ISA!" | 50 print("ERROR: Checker only supported under ARM ISA!") |
49 exit(1) 50 51 branchPred = Param.BranchPredictor(NULL, "Branch Predictor") | 51 exit(1) 52 53 branchPred = Param.BranchPredictor(NULL, "Branch Predictor") |