AtomicSimpleCPU.py (9647:5b6b315472e7) AtomicSimpleCPU.py (10381:ab8b8601b6ff)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
41from m5.params import *
42from BaseSimpleCPU import BaseSimpleCPU
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 26 unchanged lines hidden (view full) ---

35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
41from m5.params import *
42from BaseSimpleCPU import BaseSimpleCPU
43from SimPoint import SimPoint
43
44class AtomicSimpleCPU(BaseSimpleCPU):
45 """Simple CPU model executing a configurable number of
46 instructions per cycle. This model uses the simplified 'atomic'
47 memory mode."""
48
49 type = 'AtomicSimpleCPU'
50 cxx_header = "cpu/simple/atomic.hh"

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56 @classmethod
57 def support_take_over(cls):
58 return True
59
60 width = Param.Int(1, "CPU width")
61 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
62 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
63 fastmem = Param.Bool(False, "Access memory directly")
44
45class AtomicSimpleCPU(BaseSimpleCPU):
46 """Simple CPU model executing a configurable number of
47 instructions per cycle. This model uses the simplified 'atomic'
48 memory mode."""
49
50 type = 'AtomicSimpleCPU'
51 cxx_header = "cpu/simple/atomic.hh"

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57 @classmethod
58 def support_take_over(cls):
59 return True
60
61 width = Param.Int(1, "CPU width")
62 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
63 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
64 fastmem = Param.Bool(False, "Access memory directly")
64 simpoint_profile = Param.Bool(False, "Generate SimPoint BBVs")
65 simpoint_interval = Param.UInt64(100000000, "SimPoint Interval Size (insts)")
66 simpoint_profile_file = Param.String("simpoint.bb.gz", "SimPoint BBV file")
65
66 def addSimPointProbe(self, interval):
67 simpoint = SimPoint()
68 simpoint.interval = interval
69 self.probeListener = simpoint