| AtomicSimpleCPU.py (9518:8faae62af8c3) | AtomicSimpleCPU.py (9647:5b6b315472e7) |
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| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 47 unchanged lines hidden (view full) --- 56 @classmethod 57 def support_take_over(cls): 58 return True 59 60 width = Param.Int(1, "CPU width") 61 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 62 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 63 fastmem = Param.Bool(False, "Access memory directly") | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 47 unchanged lines hidden (view full) --- 56 @classmethod 57 def support_take_over(cls): 58 return True 59 60 width = Param.Int(1, "CPU width") 61 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 62 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 63 fastmem = Param.Bool(False, "Access memory directly") |
| 64 simpoint_profile = Param.Bool(False, "Generate SimPoint BBVs") 65 simpoint_interval = Param.UInt64(100000000, "SimPoint Interval Size (insts)") 66 simpoint_profile_file = Param.String("simpoint.bb.gz", "SimPoint BBV file") |
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