AtomicSimpleCPU.py (8926:570b44fe6e04) AtomicSimpleCPU.py (9338:97b4a2be1e5b)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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38#
39# Authors: Nathan Binkert
40
41from m5.params import *
42from BaseSimpleCPU import BaseSimpleCPU
43
44class AtomicSimpleCPU(BaseSimpleCPU):
45 type = 'AtomicSimpleCPU'
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 29 unchanged lines hidden (view full) ---

38#
39# Authors: Nathan Binkert
40
41from m5.params import *
42from BaseSimpleCPU import BaseSimpleCPU
43
44class AtomicSimpleCPU(BaseSimpleCPU):
45 type = 'AtomicSimpleCPU'
46 cxx_header = "cpu/simple/atomic.hh"
46 width = Param.Int(1, "CPU width")
47 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
48 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
49 fastmem = Param.Bool(False, "Access memory directly")
47 width = Param.Int(1, "CPU width")
48 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
49 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
50 fastmem = Param.Bool(False, "Access memory directly")