AtomicSimpleCPU.py (5536:17c0c17726ff) | AtomicSimpleCPU.py (5537:eaeed2bdf50d) |
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1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5 import build_env 31from BaseSimpleCPU import BaseSimpleCPU 32 33class AtomicSimpleCPU(BaseSimpleCPU): 34 type = 'AtomicSimpleCPU' 35 width = Param.Int(1, "CPU width") 36 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 37 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 21 unchanged lines hidden (view full) --- 30from m5 import build_env 31from BaseSimpleCPU import BaseSimpleCPU 32 33class AtomicSimpleCPU(BaseSimpleCPU): 34 type = 'AtomicSimpleCPU' 35 width = Param.Int(1, "CPU width") 36 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 37 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") |
38 function_trace = Param.Bool(False, "Enable function trace") 39 function_trace_start = Param.Tick(0, "Cycle to start function trace") | |
40 icache_port = Port("Instruction Port") 41 dcache_port = Port("Data Port") 42 physmem_port = Port("Physical Memory Port") 43 _mem_ports = BaseSimpleCPU._mem_ports + \ 44 ['icache_port', 'dcache_port', 'physmem_port'] | 38 icache_port = Port("Instruction Port") 39 dcache_port = Port("Data Port") 40 physmem_port = Port("Physical Memory Port") 41 _mem_ports = BaseSimpleCPU._mem_ports + \ 42 ['icache_port', 'dcache_port', 'physmem_port'] |