AtomicSimpleCPU.py (5487:f0ac4112e128) | AtomicSimpleCPU.py (5529:9ae69b9cd7fd) |
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1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.params import * 30from m5 import build_env | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.params import * 30from m5 import build_env |
31from BaseCPU import BaseCPU | 31from BaseSimpleCPU import BaseSimpleCPU |
32 | 32 |
33class AtomicSimpleCPU(BaseCPU): | 33class AtomicSimpleCPU(BaseSimpleCPU): |
34 type = 'AtomicSimpleCPU' 35 width = Param.Int(1, "CPU width") 36 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 37 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 38 function_trace = Param.Bool(False, "Enable function trace") 39 function_trace_start = Param.Tick(0, "Cycle to start function trace") 40 if build_env['FULL_SYSTEM']: 41 profile = Param.Latency('0ns', "trace the kernel stack") 42 icache_port = Port("Instruction Port") 43 dcache_port = Port("Data Port") 44 physmem_port = Port("Physical Memory Port") | 34 type = 'AtomicSimpleCPU' 35 width = Param.Int(1, "CPU width") 36 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 37 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 38 function_trace = Param.Bool(False, "Enable function trace") 39 function_trace_start = Param.Tick(0, "Cycle to start function trace") 40 if build_env['FULL_SYSTEM']: 41 profile = Param.Latency('0ns', "trace the kernel stack") 42 icache_port = Port("Instruction Port") 43 dcache_port = Port("Data Port") 44 physmem_port = Port("Physical Memory Port") |
45 _mem_ports = BaseCPU._mem_ports + \ | 45 _mem_ports = BaseSimpleCPU._mem_ports + \ |
46 ['icache_port', 'dcache_port', 'physmem_port'] | 46 ['icache_port', 'dcache_port', 'physmem_port'] |