AtomicSimpleCPU.py (5236:0050ad4fb3ef) AtomicSimpleCPU.py (5487:f0ac4112e128)
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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28
29from m5.params import *
30from m5 import build_env
31from BaseCPU import BaseCPU
32
33class AtomicSimpleCPU(BaseCPU):
34 type = 'AtomicSimpleCPU'
35 width = Param.Int(1, "CPU width")
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 19 unchanged lines hidden (view full) ---

28
29from m5.params import *
30from m5 import build_env
31from BaseCPU import BaseCPU
32
33class AtomicSimpleCPU(BaseCPU):
34 type = 'AtomicSimpleCPU'
35 width = Param.Int(1, "CPU width")
36 simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
36 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
37 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
37 function_trace = Param.Bool(False, "Enable function trace")
38 function_trace_start = Param.Tick(0, "Cycle to start function trace")
39 if build_env['FULL_SYSTEM']:
40 profile = Param.Latency('0ns', "trace the kernel stack")
41 icache_port = Port("Instruction Port")
42 dcache_port = Port("Data Port")
43 physmem_port = Port("Physical Memory Port")
44 _mem_ports = BaseCPU._mem_ports + \
45 ['icache_port', 'dcache_port', 'physmem_port']
38 function_trace = Param.Bool(False, "Enable function trace")
39 function_trace_start = Param.Tick(0, "Cycle to start function trace")
40 if build_env['FULL_SYSTEM']:
41 profile = Param.Latency('0ns', "trace the kernel stack")
42 icache_port = Port("Instruction Port")
43 dcache_port = Port("Data Port")
44 physmem_port = Port("Physical Memory Port")
45 _mem_ports = BaseCPU._mem_ports + \
46 ['icache_port', 'dcache_port', 'physmem_port']