AtomicSimpleCPU.py (4486:aaeb03a8a6e1) | AtomicSimpleCPU.py (4968:f1c856d8c460) |
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1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 width = Param.Int(1, "CPU width") 36 simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") 37 function_trace = Param.Bool(False, "Enable function trace") 38 function_trace_start = Param.Tick(0, "Cycle to start function trace") 39 if build_env['FULL_SYSTEM']: 40 profile = Param.Latency('0ns', "trace the kernel stack") 41 icache_port = Port("Instruction Port") 42 dcache_port = Port("Data Port") | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 width = Param.Int(1, "CPU width") 36 simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") 37 function_trace = Param.Bool(False, "Enable function trace") 38 function_trace_start = Param.Tick(0, "Cycle to start function trace") 39 if build_env['FULL_SYSTEM']: 40 profile = Param.Latency('0ns', "trace the kernel stack") 41 icache_port = Port("Instruction Port") 42 dcache_port = Port("Data Port") |
43 _mem_ports = ['icache_port', 'dcache_port'] | 43 physmem_port = Port("Physical Memory Port") 44 _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] |