| AtomicSimpleCPU.py (10381:ab8b8601b6ff) | AtomicSimpleCPU.py (13012:5fbc6b9c64bc) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 47 unchanged lines hidden (view full) --- 56 57 @classmethod 58 def support_take_over(cls): 59 return True 60 61 width = Param.Int(1, "CPU width") 62 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 63 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 47 unchanged lines hidden (view full) --- 56 57 @classmethod 58 def support_take_over(cls): 59 return True 60 61 width = Param.Int(1, "CPU width") 62 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 63 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") |
| 64 fastmem = Param.Bool(False, "Access memory directly") | |
| 65 66 def addSimPointProbe(self, interval): 67 simpoint = SimPoint() 68 simpoint.interval = interval 69 self.probeListener = simpoint | 64 65 def addSimPointProbe(self, interval): 66 simpoint = SimPoint() 67 simpoint.interval = interval 68 self.probeListener = simpoint |