1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 28 unchanged lines hidden (view full) --- 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Nathan Binkert 40 41from m5.params import * 42from BaseSimpleCPU import BaseSimpleCPU 43 44class AtomicSimpleCPU(BaseSimpleCPU): |
45 """Simple CPU model executing a configurable number of 46 instructions per cycle. This model uses the simplified 'atomic' 47 memory mode.""" 48 |
49 type = 'AtomicSimpleCPU' 50 cxx_header = "cpu/simple/atomic.hh" |
51 52 @classmethod 53 def memory_mode(cls): 54 return 'atomic' 55 56 @classmethod 57 def support_take_over(cls): 58 return True 59 |
60 width = Param.Int(1, "CPU width") 61 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") 62 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") 63 fastmem = Param.Bool(False, "Access memory directly") |