1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29from m5.params import *
30from BaseSimpleCPU import BaseSimpleCPU
31
32class AtomicSimpleCPU(BaseSimpleCPU):
33 type = 'AtomicSimpleCPU'
34 width = Param.Int(1, "CPU width")
35 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
36 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
37 physmem_port = MasterPort("Physical Memory Port")