1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright

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41from m5.params import *
42from BaseSimpleCPU import BaseSimpleCPU
43
44class AtomicSimpleCPU(BaseSimpleCPU):
45 type = 'AtomicSimpleCPU'
46 width = Param.Int(1, "CPU width")
47 simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
48 simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
49 fastmem = Param.Bool(False, "Access memory directly")