reg_class.hh (9920:028e4da64b42) | reg_class.hh (10934:5af8f40d8f2c) |
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1/* 2 * Copyright (c) 2013 Advanced Micro Devices, Inc. 3 * All rights reserved 4 *. 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/registers.hh" 38#include "config/the_isa.hh" 39 40/// Enumerate the classes of registers. 41enum RegClass { 42 IntRegClass, ///< Integer register 43 FloatRegClass, ///< Floating-point register 44 CCRegClass, ///< Condition-code register | 1/* 2 * Copyright (c) 2013 Advanced Micro Devices, Inc. 3 * All rights reserved 4 *. 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/registers.hh" 38#include "config/the_isa.hh" 39 40/// Enumerate the classes of registers. 41enum RegClass { 42 IntRegClass, ///< Integer register 43 FloatRegClass, ///< Floating-point register 44 CCRegClass, ///< Condition-code register |
45 VectorRegClass, ///< Vector register |
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45 MiscRegClass ///< Control (misc) register 46}; 47 48/// Number of register classes. This value is not part of the enum, 49/// because putting it there makes the compiler complain about 50/// unhandled cases in some switch statements. 51const int NumRegClasses = MiscRegClass + 1; 52 --- 18 unchanged lines hidden (view full) --- 71 int offset; 72 73 if (reg_idx < TheISA::FP_Reg_Base) { 74 cl = IntRegClass; 75 offset = 0; 76 } else if (reg_idx < TheISA::CC_Reg_Base) { 77 cl = FloatRegClass; 78 offset = TheISA::FP_Reg_Base; | 46 MiscRegClass ///< Control (misc) register 47}; 48 49/// Number of register classes. This value is not part of the enum, 50/// because putting it there makes the compiler complain about 51/// unhandled cases in some switch statements. 52const int NumRegClasses = MiscRegClass + 1; 53 --- 18 unchanged lines hidden (view full) --- 72 int offset; 73 74 if (reg_idx < TheISA::FP_Reg_Base) { 75 cl = IntRegClass; 76 offset = 0; 77 } else if (reg_idx < TheISA::CC_Reg_Base) { 78 cl = FloatRegClass; 79 offset = TheISA::FP_Reg_Base; |
79 } else if (reg_idx < TheISA::Misc_Reg_Base) { | 80 } else if (reg_idx < TheISA::Vector_Reg_Base) { |
80 // if there are no CC regs, the ISA should set 81 // CC_Reg_Base == Misc_Reg_Base so the if above 82 // never succeeds 83 cl = CCRegClass; 84 offset = TheISA::CC_Reg_Base; | 81 // if there are no CC regs, the ISA should set 82 // CC_Reg_Base == Misc_Reg_Base so the if above 83 // never succeeds 84 cl = CCRegClass; 85 offset = TheISA::CC_Reg_Base; |
86 } else if (reg_idx < TheISA::Misc_Reg_Base) { 87 cl = VectorRegClass; 88 offset = TheISA::Vector_Reg_Base; |
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85 } else { 86 cl = MiscRegClass; 87 offset = TheISA::Misc_Reg_Base; 88 } 89 90 if (rel_reg_idx) 91 *rel_reg_idx = reg_idx - offset; 92 return cl; 93} 94 95/// Map enum values to strings for debugging 96extern const char *RegClassStrings[]; 97 98 99#endif // __CPU__REG_CLASS_HH__ | 89 } else { 90 cl = MiscRegClass; 91 offset = TheISA::Misc_Reg_Base; 92 } 93 94 if (rel_reg_idx) 95 *rel_reg_idx = reg_idx - offset; 96 return cl; 97} 98 99/// Map enum values to strings for debugging 100extern const char *RegClassStrings[]; 101 102 103#endif // __CPU__REG_CLASS_HH__ |