reg_class.hh (9918:2c7219e2d999) | reg_class.hh (9920:028e4da64b42) |
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1/* 2 * Copyright (c) 2013 Advanced Micro Devices, Inc. 3 * All rights reserved 4 *. 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36 37#include "arch/registers.hh" 38#include "config/the_isa.hh" 39 40/// Enumerate the classes of registers. 41enum RegClass { 42 IntRegClass, ///< Integer register 43 FloatRegClass, ///< Floating-point register | 1/* 2 * Copyright (c) 2013 Advanced Micro Devices, Inc. 3 * All rights reserved 4 *. 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36 37#include "arch/registers.hh" 38#include "config/the_isa.hh" 39 40/// Enumerate the classes of registers. 41enum RegClass { 42 IntRegClass, ///< Integer register 43 FloatRegClass, ///< Floating-point register |
44 CCRegClass, ///< Condition-code register |
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44 MiscRegClass ///< Control (misc) register 45}; 46 47/// Number of register classes. This value is not part of the enum, 48/// because putting it there makes the compiler complain about 49/// unhandled cases in some switch statements. 50const int NumRegClasses = MiscRegClass + 1; 51 --- 15 unchanged lines hidden (view full) --- 67{ 68 assert(reg_idx < TheISA::Max_Reg_Index); 69 RegClass cl; 70 int offset; 71 72 if (reg_idx < TheISA::FP_Reg_Base) { 73 cl = IntRegClass; 74 offset = 0; | 45 MiscRegClass ///< Control (misc) register 46}; 47 48/// Number of register classes. This value is not part of the enum, 49/// because putting it there makes the compiler complain about 50/// unhandled cases in some switch statements. 51const int NumRegClasses = MiscRegClass + 1; 52 --- 15 unchanged lines hidden (view full) --- 68{ 69 assert(reg_idx < TheISA::Max_Reg_Index); 70 RegClass cl; 71 int offset; 72 73 if (reg_idx < TheISA::FP_Reg_Base) { 74 cl = IntRegClass; 75 offset = 0; |
75 } else if (reg_idx < TheISA::Misc_Reg_Base) { | 76 } else if (reg_idx < TheISA::CC_Reg_Base) { |
76 cl = FloatRegClass; 77 offset = TheISA::FP_Reg_Base; | 77 cl = FloatRegClass; 78 offset = TheISA::FP_Reg_Base; |
79 } else if (reg_idx < TheISA::Misc_Reg_Base) { 80 // if there are no CC regs, the ISA should set 81 // CC_Reg_Base == Misc_Reg_Base so the if above 82 // never succeeds 83 cl = CCRegClass; 84 offset = TheISA::CC_Reg_Base; |
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78 } else { 79 cl = MiscRegClass; 80 offset = TheISA::Misc_Reg_Base; 81 } 82 83 if (rel_reg_idx) 84 *rel_reg_idx = reg_idx - offset; 85 return cl; 86} 87 88/// Map enum values to strings for debugging 89extern const char *RegClassStrings[]; 90 91 92#endif // __CPU__REG_CLASS_HH__ | 85 } else { 86 cl = MiscRegClass; 87 offset = TheISA::Misc_Reg_Base; 88 } 89 90 if (rel_reg_idx) 91 *rel_reg_idx = reg_idx - offset; 92 return cl; 93} 94 95/// Map enum values to strings for debugging 96extern const char *RegClassStrings[]; 97 98 99#endif // __CPU__REG_CLASS_HH__ |