reg_class.hh (12106:7784fac1b159) | reg_class.hh (12109:f29e9c5418aa) |
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1/* 2 * Copyright (c) 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 25 unchanged lines hidden (view full) --- 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathanael Premillieu | 1/* 2 * Copyright (c) 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 25 unchanged lines hidden (view full) --- 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathanael Premillieu |
42 * Rekai Gonzalez |
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42 */ 43 44#ifndef __CPU__REG_CLASS_HH__ 45#define __CPU__REG_CLASS_HH__ 46 47#include <cassert> 48#include <cstddef> 49 50#include "arch/generic/types.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53 54/** Enumerate the classes of registers. */ 55enum RegClass { 56 IntRegClass, ///< Integer register 57 FloatRegClass, ///< Floating-point register | 43 */ 44 45#ifndef __CPU__REG_CLASS_HH__ 46#define __CPU__REG_CLASS_HH__ 47 48#include <cassert> 49#include <cstddef> 50 51#include "arch/generic/types.hh" 52#include "arch/registers.hh" 53#include "config/the_isa.hh" 54 55/** Enumerate the classes of registers. */ 56enum RegClass { 57 IntRegClass, ///< Integer register 58 FloatRegClass, ///< Floating-point register |
59 /** Vector Register. */ 60 VecRegClass, 61 /** Vector Register Native Elem lane. */ 62 VecElemClass, |
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58 CCRegClass, ///< Condition-code register 59 MiscRegClass ///< Control (misc) register 60}; 61 62/** Number of register classes. 63 * This value is not part of the enum, because putting it there makes the 64 * compiler complain about unhandled cases in some switch statements. 65 */ --- 4 unchanged lines hidden (view full) --- 70 * between different classes of registers. For example, a integer register with 71 * index 3 is represented by Regid(IntRegClass, 3). 72 */ 73class RegId { 74 private: 75 static const char* regClassStrings[]; 76 RegClass regClass; 77 RegIndex regIdx; | 63 CCRegClass, ///< Condition-code register 64 MiscRegClass ///< Control (misc) register 65}; 66 67/** Number of register classes. 68 * This value is not part of the enum, because putting it there makes the 69 * compiler complain about unhandled cases in some switch statements. 70 */ --- 4 unchanged lines hidden (view full) --- 75 * between different classes of registers. For example, a integer register with 76 * index 3 is represented by Regid(IntRegClass, 3). 77 */ 78class RegId { 79 private: 80 static const char* regClassStrings[]; 81 RegClass regClass; 82 RegIndex regIdx; |
83 ElemIndex elemIdx; 84 static constexpr size_t Scale = TheISA::NumVecElemPerVecReg; |
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78 public: 79 RegId() {}; 80 RegId(RegClass reg_class, RegIndex reg_idx) | 85 public: 86 RegId() {}; 87 RegId(RegClass reg_class, RegIndex reg_idx) |
81 : regClass(reg_class), regIdx(reg_idx) 82 {} | 88 : regClass(reg_class), regIdx(reg_idx), elemIdx(-1) 89 { 90 panic_if(regClass == VecElemClass, 91 "Creating vector physical index w/o element index"); 92 } |
83 | 93 |
94 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) 95 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx) 96 { 97 panic_if(regClass != VecElemClass, 98 "Creating non-vector physical index w/ element index"); 99 } 100 |
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84 bool operator==(const RegId& that) const { | 101 bool operator==(const RegId& that) const { |
85 return regClass == that.classValue() && regIdx == that.index(); | 102 return regClass == that.classValue() && regIdx == that.index() 103 && elemIdx == that.elemIndex(); |
86 } 87 88 bool operator!=(const RegId& that) const { 89 return !(*this==that); 90 } 91 92 /** Order operator. 93 * The order is required to implement maps with key type RegId 94 */ 95 bool operator<(const RegId& that) const { 96 return regClass < that.classValue() || | 104 } 105 106 bool operator!=(const RegId& that) const { 107 return !(*this==that); 108 } 109 110 /** Order operator. 111 * The order is required to implement maps with key type RegId 112 */ 113 bool operator<(const RegId& that) const { 114 return regClass < that.classValue() || |
97 (regClass == that.classValue() && regIdx < that.index()); | 115 (regClass == that.classValue() && ( 116 regIdx < that.index() || 117 (regIdx == that.index() && elemIdx < that.elemIndex()))); |
98 } 99 100 /** 101 * Return true if this register can be renamed 102 */ 103 bool isRenameable() const 104 { 105 return regClass != MiscRegClass; --- 9 unchanged lines hidden (view full) --- 115 116 /** @return true if it is an integer physical register. */ 117 bool isIntReg() const { return regClass == IntRegClass; } 118 119 /** @return true if it is a floating-point physical register. */ 120 bool isFloatReg() const { return regClass == FloatRegClass; } 121 122 /** @Return true if it is a condition-code physical register. */ | 118 } 119 120 /** 121 * Return true if this register can be renamed 122 */ 123 bool isRenameable() const 124 { 125 return regClass != MiscRegClass; --- 9 unchanged lines hidden (view full) --- 135 136 /** @return true if it is an integer physical register. */ 137 bool isIntReg() const { return regClass == IntRegClass; } 138 139 /** @return true if it is a floating-point physical register. */ 140 bool isFloatReg() const { return regClass == FloatRegClass; } 141 142 /** @Return true if it is a condition-code physical register. */ |
143 bool isVecReg() const { return regClass == VecRegClass; } 144 145 /** @Return true if it is a condition-code physical register. */ 146 bool isVecElem() const { return regClass == VecElemClass; } 147 148 /** @Return true if it is a condition-code physical register. */ |
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123 bool isCCReg() const { return regClass == CCRegClass; } 124 125 /** @Return true if it is a condition-code physical register. */ 126 bool isMiscReg() const { return regClass == MiscRegClass; } 127 | 149 bool isCCReg() const { return regClass == CCRegClass; } 150 151 /** @Return true if it is a condition-code physical register. */ 152 bool isMiscReg() const { return regClass == MiscRegClass; } 153 |
154 /** 155 * Return true if this register can be renamed 156 */ 157 bool isRenameable() 158 { 159 return regClass != MiscRegClass; 160 } 161 |
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128 /** Index accessors */ 129 /** @{ */ 130 const RegIndex& index() const { return regIdx; } 131 RegIndex& index() { return regIdx; } 132 133 /** Index flattening. 134 * Required to be able to use a vector for the register mapping. 135 */ 136 inline RegIndex flatIndex() const; 137 /** @} */ 138 | 162 /** Index accessors */ 163 /** @{ */ 164 const RegIndex& index() const { return regIdx; } 165 RegIndex& index() { return regIdx; } 166 167 /** Index flattening. 168 * Required to be able to use a vector for the register mapping. 169 */ 170 inline RegIndex flatIndex() const; 171 /** @} */ 172 |
173 /** Elem accessor */ 174 const RegIndex& elemIndex() const { return elemIdx; } |
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139 /** Class accessor */ 140 const RegClass& classValue() const { return regClass; } 141 /** Return a const char* with the register class name. */ 142 const char* className() const { return regClassStrings[regClass]; } 143 144 friend std::ostream& 145 operator<<(std::ostream& os, const RegId& rid) { 146 return os << rid.className() << "{" << rid.index() << "}"; 147 } 148}; 149#endif // __CPU__REG_CLASS_HH__ | 175 /** Class accessor */ 176 const RegClass& classValue() const { return regClass; } 177 /** Return a const char* with the register class name. */ 178 const char* className() const { return regClassStrings[regClass]; } 179 180 friend std::ostream& 181 operator<<(std::ostream& os, const RegId& rid) { 182 return os << rid.className() << "{" << rid.index() << "}"; 183 } 184}; 185#endif // __CPU__REG_CLASS_HH__ |