reg_class.hh (12104:edd63f9c6184) reg_class.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include <cassert>
48#include <cstddef>
49
50#include "arch/generic/types.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 37 unchanged lines hidden (view full) ---

46
47#include <cassert>
48#include <cstddef>
49
50#include "arch/generic/types.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53
54/// Enumerate the classes of registers.
54/** Enumerate the classes of registers. */
55enum RegClass {
56 IntRegClass, ///< Integer register
57 FloatRegClass, ///< Floating-point register
58 CCRegClass, ///< Condition-code register
59 MiscRegClass ///< Control (misc) register
60};
61
55enum RegClass {
56 IntRegClass, ///< Integer register
57 FloatRegClass, ///< Floating-point register
58 CCRegClass, ///< Condition-code register
59 MiscRegClass ///< Control (misc) register
60};
61
62/// Number of register classes. This value is not part of the enum,
63/// because putting it there makes the compiler complain about
64/// unhandled cases in some switch statements.
62/** Number of register classes.
63 * This value is not part of the enum, because putting it there makes the
64 * compiler complain about unhandled cases in some switch statements.
65 */
65const int NumRegClasses = MiscRegClass + 1;
66
66const int NumRegClasses = MiscRegClass + 1;
67
67/// Register ID: describe an architectural register with its class and index.
68/// This structure is used instead of just the register index to disambiguate
69/// between different classes of registers.
70/// For example, a integer register with index 3 is represented by
71/// Regid(IntRegClass, 3).
72struct RegId {
68/** Register ID: describe an architectural register with its class and index.
69 * This structure is used instead of just the register index to disambiguate
70 * between different classes of registers. For example, a integer register with
71 * index 3 is represented by Regid(IntRegClass, 3).
72 */
73class RegId {
74 private:
75 static const char* regClassStrings[];
73 RegClass regClass;
74 RegIndex regIdx;
76 RegClass regClass;
77 RegIndex regIdx;
78 public:
75 RegId() {};
76 RegId(RegClass reg_class, RegIndex reg_idx)
77 : regClass(reg_class), regIdx(reg_idx)
78 {}
79
80 bool operator==(const RegId& that) const {
79 RegId() {};
80 RegId(RegClass reg_class, RegIndex reg_idx)
81 : regClass(reg_class), regIdx(reg_idx)
82 {}
83
84 bool operator==(const RegId& that) const {
81 return regClass == that.regClass && regIdx == that.regIdx;
85 return regClass == that.classValue() && regIdx == that.index();
82 }
83
84 bool operator!=(const RegId& that) const {
85 return !(*this==that);
86 }
87
86 }
87
88 bool operator!=(const RegId& that) const {
89 return !(*this==that);
90 }
91
88 /**
89 * Returns true if this register is a zero register (needs to have a
90 * constant zero value throughout the execution)
92 /** Order operator.
93 * The order is required to implement maps with key type RegId
91 */
94 */
92 bool isZeroReg() const
93 {
94 return (regIdx == TheISA::ZeroReg &&
95 (regClass == IntRegClass ||
96 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass)));
95 bool operator<(const RegId& that) const {
96 return regClass < that.classValue() ||
97 (regClass == that.classValue() && regIdx < that.index());
97 }
98
99 /**
100 * Return true if this register can be renamed
101 */
98 }
99
100 /**
101 * Return true if this register can be renamed
102 */
102 bool isRenameable()
103 bool isRenameable() const
103 {
104 return regClass != MiscRegClass;
105 }
106
104 {
105 return regClass != MiscRegClass;
106 }
107
107 static const RegId zeroReg;
108};
108 /**
109 * Check if this is the zero register.
110 * Returns true if this register is a zero register (needs to have a
111 * constant zero value throughout the execution).
112 */
109
113
110/// Map enum values to strings for debugging
111extern const char *RegClassStrings[];
114 inline bool isZeroReg() const;
115
116 /** @return true if it is an integer physical register. */
117 bool isIntReg() const { return regClass == IntRegClass; }
118
119 /** @return true if it is a floating-point physical register. */
120 bool isFloatReg() const { return regClass == FloatRegClass; }
121
122 /** @Return true if it is a condition-code physical register. */
123 bool isCCReg() const { return regClass == CCRegClass; }
124
125 /** @Return true if it is a condition-code physical register. */
126 bool isMiscReg() const { return regClass == MiscRegClass; }
127
128 /** Index accessors */
129 /** @{ */
130 const RegIndex& index() const { return regIdx; }
131 RegIndex& index() { return regIdx; }
132
133 /** Index flattening.
134 * Required to be able to use a vector for the register mapping.
135 */
136 inline RegIndex flatIndex() const;
137 /** @} */
138
139 /** Class accessor */
140 const RegClass& classValue() const { return regClass; }
141 /** Return a const char* with the register class name. */
142 const char* className() const { return regClassStrings[regClass]; }
143
144 friend std::ostream&
145 operator<<(std::ostream& os, const RegId& rid) {
146 return os << rid.className() << "{" << rid.index() << "}";
147 }
148};
112#endif // __CPU__REG_CLASS_HH__
149#endif // __CPU__REG_CLASS_HH__