indirect.hh (13810:f50e3b82df73) indirect.hh (13957:25e9c77a8a99)
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Mitch Hayenga
29 */
30
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Mitch Hayenga
29 */
30
31#ifndef __CPU_PRED_INDIRECT_HH__
32#define __CPU_PRED_INDIRECT_HH__
31#ifndef __CPU_PRED_INDIRECT_BASE_HH__
32#define __CPU_PRED_INDIRECT_BASE_HH__
33
33
34#include <deque>
35
36#include "arch/isa_traits.hh"
37#include "config/the_isa.hh"
38#include "cpu/inst_seq.hh"
34#include "arch/isa_traits.hh"
35#include "config/the_isa.hh"
36#include "cpu/inst_seq.hh"
37#include "params/IndirectPredictor.hh"
38#include "sim/sim_object.hh"
39
39
40class IndirectPredictor
40class IndirectPredictor : public SimObject
41{
42 public:
41{
42 public:
43 IndirectPredictor(bool hash_ghr, bool hash_targets,
44 unsigned num_sets, unsigned num_ways,
45 unsigned tag_bits, unsigned path_len,
46 unsigned inst_shift, unsigned num_threads,
47 unsigned ghr_size);
48 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
49 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
50 ThreadID tid);
51 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
52 void squash(InstSeqNum seq_num, ThreadID tid);
53 void recordTarget(InstSeqNum seq_num, void * indirect_history,
54 const TheISA::PCState& target, ThreadID tid);
55 void genIndirectInfo(ThreadID tid, void* & indirect_history);
56 void updateDirectionInfo(ThreadID tid, bool actually_taken);
57 void deleteIndirectInfo(ThreadID tid, void * indirect_history);
58 void changeDirectionPrediction(ThreadID tid, void * indirect_history,
59 bool actually_taken);
60
43
61 private:
62 const bool hashGHR;
63 const bool hashTargets;
64 const unsigned numSets;
65 const unsigned numWays;
66 const unsigned tagBits;
67 const unsigned pathLength;
68 const unsigned instShift;
69 const unsigned ghrNumBits;
70 const unsigned ghrMask;
44 typedef IndirectPredictorParams Params;
71
45
72 struct IPredEntry
46 IndirectPredictor(const Params *params)
47 : SimObject(params)
73 {
48 {
74 IPredEntry() : tag(0), target(0) { }
75 Addr tag;
76 TheISA::PCState target;
77 };
49 }
78
50
79 std::vector<std::vector<IPredEntry> > targetCache;
80
81 Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
82 Addr getTag(Addr br_addr);
83
84 struct HistoryEntry
85 {
86 HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
87 : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
88 Addr pcAddr;
89 Addr targetAddr;
90 InstSeqNum seqNum;
91 };
92
93
94 struct ThreadInfo {
95 ThreadInfo() : headHistEntry(0), ghr(0) { }
96
97 std::deque<HistoryEntry> pathHist;
98 unsigned headHistEntry;
99 unsigned ghr;
100 };
101
102 std::vector<ThreadInfo> threadInfo;
51 virtual bool lookup(Addr br_addr, TheISA::PCState& br_target,
52 ThreadID tid) = 0;
53 virtual void recordIndirect(Addr br_addr, Addr tgt_addr,
54 InstSeqNum seq_num, ThreadID tid) = 0;
55 virtual void commit(InstSeqNum seq_num, ThreadID tid,
56 void * indirect_history) = 0;
57 virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
58 virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
59 const TheISA::PCState& target, ThreadID tid) = 0;
60 virtual void genIndirectInfo(ThreadID tid, void* & indirect_history) = 0;
61 virtual void updateDirectionInfo(ThreadID tid, bool actually_taken) = 0;
62 virtual void deleteIndirectInfo(ThreadID tid, void * indirect_history) = 0;
63 virtual void changeDirectionPrediction(ThreadID tid,
64 void * indirect_history,
65 bool actually_taken) = 0;
103};
104
66};
67
105#endif // __CPU_PRED_INDIRECT_HH__
68#endif // __CPU_PRED_INDIRECT_BASE_HH__