indirect.hh (13654:dc3878f03a0c) indirect.hh (13810:f50e3b82df73)
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "cpu/inst_seq.hh"
39
40class IndirectPredictor
41{
42 public:
43 IndirectPredictor(bool hash_ghr, bool hash_targets,
44 unsigned num_sets, unsigned num_ways,
45 unsigned tag_bits, unsigned path_len,
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 29 unchanged lines hidden (view full) ---

38#include "cpu/inst_seq.hh"
39
40class IndirectPredictor
41{
42 public:
43 IndirectPredictor(bool hash_ghr, bool hash_targets,
44 unsigned num_sets, unsigned num_ways,
45 unsigned tag_bits, unsigned path_len,
46 unsigned inst_shift, unsigned num_threads);
46 unsigned inst_shift, unsigned num_threads,
47 unsigned ghr_size);
47 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
48 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
49 ThreadID tid);
50 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
51 void squash(InstSeqNum seq_num, ThreadID tid);
48 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
49 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
50 ThreadID tid);
51 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
52 void squash(InstSeqNum seq_num, ThreadID tid);
52 void recordTarget(InstSeqNum seq_num, const TheISA::PCState& target,
53 ThreadID tid);
54 void updateDirectionInfo(ThreadID tid, bool taken,
55 void* & indirect_history);
53 void recordTarget(InstSeqNum seq_num, void * indirect_history,
54 const TheISA::PCState& target, ThreadID tid);
55 void genIndirectInfo(ThreadID tid, void* & indirect_history);
56 void updateDirectionInfo(ThreadID tid, bool actually_taken);
57 void deleteIndirectInfo(ThreadID tid, void * indirect_history);
56 void changeDirectionPrediction(ThreadID tid, void * indirect_history,
57 bool actually_taken);
58 void changeDirectionPrediction(ThreadID tid, void * indirect_history,
59 bool actually_taken);
58 void deleteDirectionInfo(ThreadID tid, void * indirect_history);
59
60 private:
61 const bool hashGHR;
62 const bool hashTargets;
63 const unsigned numSets;
64 const unsigned numWays;
65 const unsigned tagBits;
66 const unsigned pathLength;
67 const unsigned instShift;
60
61 private:
62 const bool hashGHR;
63 const bool hashTargets;
64 const unsigned numSets;
65 const unsigned numWays;
66 const unsigned tagBits;
67 const unsigned pathLength;
68 const unsigned instShift;
69 const unsigned ghrNumBits;
70 const unsigned ghrMask;
68
69 struct IPredEntry
70 {
71 IPredEntry() : tag(0), target(0) { }
72 Addr tag;
73 TheISA::PCState target;
74 };
75

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72 struct IPredEntry
73 {
74 IPredEntry() : tag(0), target(0) { }
75 Addr tag;
76 TheISA::PCState target;
77 };
78

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