btb.cc (11425:e24d92c62860) | btb.cc (11429:cf5af0cc3be4) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 31#include "base/intmath.hh" 32#include "base/trace.hh" 33#include "cpu/pred/btb.hh" 34#include "debug/Fetch.hh" 35 36DefaultBTB::DefaultBTB(unsigned _numEntries, 37 unsigned _tagBits, | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 31#include "base/intmath.hh" 32#include "base/trace.hh" 33#include "cpu/pred/btb.hh" 34#include "debug/Fetch.hh" 35 36DefaultBTB::DefaultBTB(unsigned _numEntries, 37 unsigned _tagBits, |
38 unsigned _instShiftAmt, 39 unsigned _num_threads) | 38 unsigned _instShiftAmt) |
40 : numEntries(_numEntries), 41 tagBits(_tagBits), | 39 : numEntries(_numEntries), 40 tagBits(_tagBits), |
42 instShiftAmt(_instShiftAmt), 43 log2NumThreads(floorLog2(_num_threads)) | 41 instShiftAmt(_instShiftAmt) |
44{ 45 DPRINTF(Fetch, "BTB: Creating BTB object.\n"); 46 47 if (!isPowerOf2(numEntries)) { 48 fatal("BTB entries is not a power of 2!"); 49 } 50 51 btb.resize(numEntries); --- 14 unchanged lines hidden (view full) --- 66{ 67 for (unsigned i = 0; i < numEntries; ++i) { 68 btb[i].valid = false; 69 } 70} 71 72inline 73unsigned | 42{ 43 DPRINTF(Fetch, "BTB: Creating BTB object.\n"); 44 45 if (!isPowerOf2(numEntries)) { 46 fatal("BTB entries is not a power of 2!"); 47 } 48 49 btb.resize(numEntries); --- 14 unchanged lines hidden (view full) --- 64{ 65 for (unsigned i = 0; i < numEntries; ++i) { 66 btb[i].valid = false; 67 } 68} 69 70inline 71unsigned |
74DefaultBTB::getIndex(Addr instPC, ThreadID tid) | 72DefaultBTB::getIndex(Addr instPC) |
75{ 76 // Need to shift PC over by the word offset. | 73{ 74 // Need to shift PC over by the word offset. |
77 return ((instPC >> instShiftAmt) 78 ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads))) 79 & idxMask; | 75 return (instPC >> instShiftAmt) & idxMask; |
80} 81 82inline 83Addr 84DefaultBTB::getTag(Addr instPC) 85{ 86 return (instPC >> tagShiftAmt) & tagMask; 87} 88 89bool 90DefaultBTB::valid(Addr instPC, ThreadID tid) 91{ | 76} 77 78inline 79Addr 80DefaultBTB::getTag(Addr instPC) 81{ 82 return (instPC >> tagShiftAmt) & tagMask; 83} 84 85bool 86DefaultBTB::valid(Addr instPC, ThreadID tid) 87{ |
92 unsigned btb_idx = getIndex(instPC, tid); | 88 unsigned btb_idx = getIndex(instPC); |
93 94 Addr inst_tag = getTag(instPC); 95 96 assert(btb_idx < numEntries); 97 98 if (btb[btb_idx].valid 99 && inst_tag == btb[btb_idx].tag 100 && btb[btb_idx].tid == tid) { --- 4 unchanged lines hidden (view full) --- 105} 106 107// @todo Create some sort of return struct that has both whether or not the 108// address is valid, and also the address. For now will just use addr = 0 to 109// represent invalid entry. 110TheISA::PCState 111DefaultBTB::lookup(Addr instPC, ThreadID tid) 112{ | 89 90 Addr inst_tag = getTag(instPC); 91 92 assert(btb_idx < numEntries); 93 94 if (btb[btb_idx].valid 95 && inst_tag == btb[btb_idx].tag 96 && btb[btb_idx].tid == tid) { --- 4 unchanged lines hidden (view full) --- 101} 102 103// @todo Create some sort of return struct that has both whether or not the 104// address is valid, and also the address. For now will just use addr = 0 to 105// represent invalid entry. 106TheISA::PCState 107DefaultBTB::lookup(Addr instPC, ThreadID tid) 108{ |
113 unsigned btb_idx = getIndex(instPC, tid); | 109 unsigned btb_idx = getIndex(instPC); |
114 115 Addr inst_tag = getTag(instPC); 116 117 assert(btb_idx < numEntries); 118 119 if (btb[btb_idx].valid 120 && inst_tag == btb[btb_idx].tag 121 && btb[btb_idx].tid == tid) { 122 return btb[btb_idx].target; 123 } else { 124 return 0; 125 } 126} 127 128void 129DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid) 130{ | 110 111 Addr inst_tag = getTag(instPC); 112 113 assert(btb_idx < numEntries); 114 115 if (btb[btb_idx].valid 116 && inst_tag == btb[btb_idx].tag 117 && btb[btb_idx].tid == tid) { 118 return btb[btb_idx].target; 119 } else { 120 return 0; 121 } 122} 123 124void 125DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid) 126{ |
131 unsigned btb_idx = getIndex(instPC, tid); | 127 unsigned btb_idx = getIndex(instPC); |
132 133 assert(btb_idx < numEntries); 134 135 btb[btb_idx].tid = tid; 136 btb[btb_idx].valid = true; 137 btb[btb_idx].target = target; 138 btb[btb_idx].tag = getTag(instPC); 139} | 128 129 assert(btb_idx < numEntries); 130 131 btb[btb_idx].tid = tid; 132 btb[btb_idx].valid = true; 133 btb[btb_idx].target = target; 134 btb[btb_idx].tag = getTag(instPC); 135} |