1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
| |
30 */
31
32#ifndef __CPU__OP_CLASS_HH__
33#define __CPU__OP_CLASS_HH__
34
35/**
36 * @file
37 * Definition of operation classes.
38 */
39
40/**
41 * Instruction operation classes. These classes are used for
42 * assigning instructions to functional units.
43 */
44enum OpClass {
45 No_OpClass = 0, ///< Instruction does not use a functional unit
46 IntAluOp, ///< Integer ALU operaton (add/sub/logical)
47 IntMultOp, ///< Integer multiply
48 IntDivOp, ///< Integer divide
49 FloatAddOp, ///< Floating point add/subtract
50 FloatCmpOp, ///< Floating point comparison
51 FloatCvtOp, ///< Floating point<->integer conversion
52 FloatMultOp, ///< Floating point multiply
53 FloatDivOp, ///< Floating point divide
54 FloatSqrtOp, ///< Floating point square root
55 MemReadOp, ///< Memory read port
56 MemWriteOp, ///< Memory write port
57 IprAccessOp, ///< Internal Processor Register read/write port
58 InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
59 Num_OpClasses ///< Total number of operation classes
60};
61
62/**
63 * Array mapping OpClass enum values to strings. Defined in op_class.cc.
64 */
| 27 */
28
29#ifndef __CPU__OP_CLASS_HH__
30#define __CPU__OP_CLASS_HH__
31
32/**
33 * @file
34 * Definition of operation classes.
35 */
36
37/**
38 * Instruction operation classes. These classes are used for
39 * assigning instructions to functional units.
40 */
41enum OpClass {
42 No_OpClass = 0, ///< Instruction does not use a functional unit
43 IntAluOp, ///< Integer ALU operaton (add/sub/logical)
44 IntMultOp, ///< Integer multiply
45 IntDivOp, ///< Integer divide
46 FloatAddOp, ///< Floating point add/subtract
47 FloatCmpOp, ///< Floating point comparison
48 FloatCvtOp, ///< Floating point<->integer conversion
49 FloatMultOp, ///< Floating point multiply
50 FloatDivOp, ///< Floating point divide
51 FloatSqrtOp, ///< Floating point square root
52 MemReadOp, ///< Memory read port
53 MemWriteOp, ///< Memory write port
54 IprAccessOp, ///< Internal Processor Register read/write port
55 InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
56 Num_OpClasses ///< Total number of operation classes
57};
58
59/**
60 * Array mapping OpClass enum values to strings. Defined in op_class.cc.
61 */
|
65extern const char *opClassStrings[];
| 62extern const char *opClassStrings[Num_OpClasses];
|
66
67#endif // __CPU__OP_CLASS_HH__
| 63
64#endif // __CPU__OP_CLASS_HH__
|