1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_THREAD_STATE_HH__
44#define __CPU_O3_THREAD_STATE_HH__
45
46#include "base/callback.hh"
47#include "base/output.hh"
48#include "cpu/thread_context.hh"
49#include "cpu/thread_state.hh"
50#include "sim/full_system.hh"
51#include "sim/sim_exit.hh"
52
53class EndQuiesceEvent;
54class Event;
55class FunctionalMemory;
56class FunctionProfile;
57class Process;
58class ProfileNode;
59
60/**
61 * Class that has various thread state, such as the status, the
62 * current instruction being processed, whether or not the thread has
63 * a trap pending or is being externally updated, the ThreadContext
64 * pointer, etc. It also handles anything related to a specific
65 * thread's process, such as syscalls and checking valid addresses.
66 */
67template <class Impl>
68struct O3ThreadState : public ThreadState {
69 typedef ThreadContext::Status Status;
70 typedef typename Impl::O3CPU O3CPU;
71
72 private:
73 /** Pointer to the CPU. */
74 O3CPU *cpu;
75 public:
76 /* This variable controls if writes to a thread context should cause a all
77 * dynamic/speculative state to be thrown away. Nominally this is the
78 * desired behavior because the external thread context write has updated
79 * some state that could be used by an inflight instruction, however there
80 * are some cases like in a fault/trap handler where this behavior would
81 * lead to successive restarts and forward progress couldn't be made. This
82 * variable controls if the squashing will occur.
83 */
84 bool noSquashFromTC;
85
86 /** Whether or not the thread is currently waiting on a trap, and
87 * thus able to be externally updated without squashing.
88 */
89 bool trapPending;
90
91 O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
92 : ThreadState(_cpu, _thread_num, _process),
93 cpu(_cpu), noSquashFromTC(false), trapPending(false),
94 tc(nullptr)
95 {
96 if (!FullSystem)
97 return;
98
99 if (cpu->params()->profile) {
100 profile = new FunctionProfile(
101 cpu->params()->system->kernelSymtab);
102 Callback *cb =
103 new MakeCallback<O3ThreadState,
104 &O3ThreadState::dumpFuncProfile>(this);
105 registerExitCallback(cb);
106 }
107
108 // let's fill with a dummy node for now so we don't get a segfault
109 // on the first cycle when there's no node available.
110 static ProfileNode dummyNode;
111 profileNode = &dummyNode;
112 profilePC = 3;
113 }
114
115 void serialize(CheckpointOut &cp) const override
116 {
117 ThreadState::serialize(cp);
118 // Use the ThreadContext serialization helper to serialize the
119 // TC.
120 ::serialize(*tc, cp);
121 }
122
123 void unserialize(CheckpointIn &cp) override
124 {
125 // Prevent squashing - we don't have any instructions in
126 // flight that we need to squash since we just instantiated a
127 // clean system.
128 noSquashFromTC = true;
129 ThreadState::unserialize(cp);
130 // Use the ThreadContext serialization helper to unserialize
131 // the TC.
132 ::unserialize(*tc, cp);
133 noSquashFromTC = false;
134 }
135
136 /** Pointer to the ThreadContext of this thread. */
137 ThreadContext *tc;
138
139 /** Returns a pointer to the TC of this thread. */
140 ThreadContext *getTC() { return tc; }
141
142 /** Handles the syscall. */
143 void syscall(int64_t callnum) { process->syscall(callnum, tc); }
144
145 void dumpFuncProfile()
146 {
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_THREAD_STATE_HH__
44#define __CPU_O3_THREAD_STATE_HH__
45
46#include "base/callback.hh"
47#include "base/output.hh"
48#include "cpu/thread_context.hh"
49#include "cpu/thread_state.hh"
50#include "sim/full_system.hh"
51#include "sim/sim_exit.hh"
52
53class EndQuiesceEvent;
54class Event;
55class FunctionalMemory;
56class FunctionProfile;
57class Process;
58class ProfileNode;
59
60/**
61 * Class that has various thread state, such as the status, the
62 * current instruction being processed, whether or not the thread has
63 * a trap pending or is being externally updated, the ThreadContext
64 * pointer, etc. It also handles anything related to a specific
65 * thread's process, such as syscalls and checking valid addresses.
66 */
67template <class Impl>
68struct O3ThreadState : public ThreadState {
69 typedef ThreadContext::Status Status;
70 typedef typename Impl::O3CPU O3CPU;
71
72 private:
73 /** Pointer to the CPU. */
74 O3CPU *cpu;
75 public:
76 /* This variable controls if writes to a thread context should cause a all
77 * dynamic/speculative state to be thrown away. Nominally this is the
78 * desired behavior because the external thread context write has updated
79 * some state that could be used by an inflight instruction, however there
80 * are some cases like in a fault/trap handler where this behavior would
81 * lead to successive restarts and forward progress couldn't be made. This
82 * variable controls if the squashing will occur.
83 */
84 bool noSquashFromTC;
85
86 /** Whether or not the thread is currently waiting on a trap, and
87 * thus able to be externally updated without squashing.
88 */
89 bool trapPending;
90
91 O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
92 : ThreadState(_cpu, _thread_num, _process),
93 cpu(_cpu), noSquashFromTC(false), trapPending(false),
94 tc(nullptr)
95 {
96 if (!FullSystem)
97 return;
98
99 if (cpu->params()->profile) {
100 profile = new FunctionProfile(
101 cpu->params()->system->kernelSymtab);
102 Callback *cb =
103 new MakeCallback<O3ThreadState,
104 &O3ThreadState::dumpFuncProfile>(this);
105 registerExitCallback(cb);
106 }
107
108 // let's fill with a dummy node for now so we don't get a segfault
109 // on the first cycle when there's no node available.
110 static ProfileNode dummyNode;
111 profileNode = &dummyNode;
112 profilePC = 3;
113 }
114
115 void serialize(CheckpointOut &cp) const override
116 {
117 ThreadState::serialize(cp);
118 // Use the ThreadContext serialization helper to serialize the
119 // TC.
120 ::serialize(*tc, cp);
121 }
122
123 void unserialize(CheckpointIn &cp) override
124 {
125 // Prevent squashing - we don't have any instructions in
126 // flight that we need to squash since we just instantiated a
127 // clean system.
128 noSquashFromTC = true;
129 ThreadState::unserialize(cp);
130 // Use the ThreadContext serialization helper to unserialize
131 // the TC.
132 ::unserialize(*tc, cp);
133 noSquashFromTC = false;
134 }
135
136 /** Pointer to the ThreadContext of this thread. */
137 ThreadContext *tc;
138
139 /** Returns a pointer to the TC of this thread. */
140 ThreadContext *getTC() { return tc; }
141
142 /** Handles the syscall. */
143 void syscall(int64_t callnum) { process->syscall(callnum, tc); }
144
145 void dumpFuncProfile()
146 {
|