thread_context_impl.hh (8232:b28d06a175be) thread_context_impl.hh (8518:9c87727099ce)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 337 unchanged lines hidden (view full) ---

346 // Squash if we're not already in a state update mode.
347 if (!thread->trapPending && !thread->inSyscall) {
348 cpu->squashFromTC(thread->threadId());
349 }
350}
351
352template <class Impl>
353void
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 337 unchanged lines hidden (view full) ---

346 // Squash if we're not already in a state update mode.
347 if (!thread->trapPending && !thread->inSyscall) {
348 cpu->squashFromTC(thread->threadId());
349 }
350}
351
352template <class Impl>
353void
354O3ThreadContext::setMiscReg(int misc_reg,
355 const MiscReg &val)
354O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
356{
357 cpu->setMiscReg(misc_reg, val, thread->threadId());
358
359 // Squash if we're not already in a state update mode.
360 if (!thread->trapPending && !thread->inSyscall) {
361 cpu->squashFromTC(thread->threadId());
362 }
363}
364
355{
356 cpu->setMiscReg(misc_reg, val, thread->threadId());
357
358 // Squash if we're not already in a state update mode.
359 if (!thread->trapPending && !thread->inSyscall) {
360 cpu->squashFromTC(thread->threadId());
361 }
362}
363