thread_context_impl.hh (6221:58a3c04e6344) thread_context_impl.hh (6313:95f69a436c82)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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267void
268O3ThreadContext<Impl>::clearArchRegs()
269{}
270
271template <class Impl>
272uint64_t
273O3ThreadContext<Impl>::readIntReg(int reg_idx)
274{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 258 unchanged lines hidden (view full) ---

267void
268O3ThreadContext<Impl>::clearArchRegs()
269{}
270
271template <class Impl>
272uint64_t
273O3ThreadContext<Impl>::readIntReg(int reg_idx)
274{
275 reg_idx = TheISA::flattenIntIndex(this, reg_idx);
275 reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
276 return cpu->readArchIntReg(reg_idx, thread->threadId());
277}
278
279template <class Impl>
280TheISA::FloatReg
281O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
282{
276 return cpu->readArchIntReg(reg_idx, thread->threadId());
277}
278
279template <class Impl>
280TheISA::FloatReg
281O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
282{
283 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
283 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
284 switch(width) {
285 case 32:
286 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
287 case 64:
288 return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
289 default:
290 panic("Unsupported width!");
291 return 0;
292 }
293}
294
295template <class Impl>
296TheISA::FloatReg
297O3ThreadContext<Impl>::readFloatReg(int reg_idx)
298{
284 switch(width) {
285 case 32:
286 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
287 case 64:
288 return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
289 default:
290 panic("Unsupported width!");
291 return 0;
292 }
293}
294
295template <class Impl>
296TheISA::FloatReg
297O3ThreadContext<Impl>::readFloatReg(int reg_idx)
298{
299 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
299 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
300 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
301}
302
303template <class Impl>
304TheISA::FloatRegBits
305O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
306{
307 DPRINTF(Fault, "Reading floatint register through the TC!\n");
300 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
301}
302
303template <class Impl>
304TheISA::FloatRegBits
305O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
306{
307 DPRINTF(Fault, "Reading floatint register through the TC!\n");
308 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
308 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
309 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
310}
311
312template <class Impl>
313TheISA::FloatRegBits
314O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
315{
309 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
310}
311
312template <class Impl>
313TheISA::FloatRegBits
314O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
315{
316 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
316 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
317 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
318}
319
320template <class Impl>
321void
322O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
323{
317 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
318}
319
320template <class Impl>
321void
322O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
323{
324 reg_idx = TheISA::flattenIntIndex(this, reg_idx);
324 reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
325 cpu->setArchIntReg(reg_idx, val, thread->threadId());
326
327 // Squash if we're not already in a state update mode.
328 if (!thread->trapPending && !thread->inSyscall) {
329 cpu->squashFromTC(thread->threadId());
330 }
331}
332
333template <class Impl>
334void
335O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
336{
325 cpu->setArchIntReg(reg_idx, val, thread->threadId());
326
327 // Squash if we're not already in a state update mode.
328 if (!thread->trapPending && !thread->inSyscall) {
329 cpu->squashFromTC(thread->threadId());
330 }
331}
332
333template <class Impl>
334void
335O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
336{
337 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
337 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
338 switch(width) {
339 case 32:
340 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
341 break;
342 case 64:
343 cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
344 break;
345 }
346
347 // Squash if we're not already in a state update mode.
348 if (!thread->trapPending && !thread->inSyscall) {
349 cpu->squashFromTC(thread->threadId());
350 }
351}
352
353template <class Impl>
354void
355O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
356{
338 switch(width) {
339 case 32:
340 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
341 break;
342 case 64:
343 cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
344 break;
345 }
346
347 // Squash if we're not already in a state update mode.
348 if (!thread->trapPending && !thread->inSyscall) {
349 cpu->squashFromTC(thread->threadId());
350 }
351}
352
353template <class Impl>
354void
355O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
356{
357 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
357 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
358 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
359
360 if (!thread->trapPending && !thread->inSyscall) {
361 cpu->squashFromTC(thread->threadId());
362 }
363}
364
365template <class Impl>
366void
367O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
368 int width)
369{
370 DPRINTF(Fault, "Setting floatint register through the TC!\n");
358 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
359
360 if (!thread->trapPending && !thread->inSyscall) {
361 cpu->squashFromTC(thread->threadId());
362 }
363}
364
365template <class Impl>
366void
367O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
368 int width)
369{
370 DPRINTF(Fault, "Setting floatint register through the TC!\n");
371 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
371 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
372 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
373
374 // Squash if we're not already in a state update mode.
375 if (!thread->trapPending && !thread->inSyscall) {
376 cpu->squashFromTC(thread->threadId());
377 }
378}
379
380template <class Impl>
381void
382O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
383{
372 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
373
374 // Squash if we're not already in a state update mode.
375 if (!thread->trapPending && !thread->inSyscall) {
376 cpu->squashFromTC(thread->threadId());
377 }
378}
379
380template <class Impl>
381void
382O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
383{
384 reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
384 reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
385 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
386
387 // Squash if we're not already in a state update mode.
388 if (!thread->trapPending && !thread->inSyscall) {
389 cpu->squashFromTC(thread->threadId());
390 }
391}
392

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434
435 // Squash if we're not already in a state update mode.
436 if (!thread->trapPending && !thread->inSyscall) {
437 cpu->squashFromTC(thread->threadId());
438 }
439}
440
441template <class Impl>
385 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
386
387 // Squash if we're not already in a state update mode.
388 if (!thread->trapPending && !thread->inSyscall) {
389 cpu->squashFromTC(thread->threadId());
390 }
391}
392

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434
435 // Squash if we're not already in a state update mode.
436 if (!thread->trapPending && !thread->inSyscall) {
437 cpu->squashFromTC(thread->threadId());
438 }
439}
440
441template <class Impl>
442int
443O3ThreadContext<Impl>::flattenIntIndex(int reg)
444{
445 return cpu->isa[thread->threadId()].flattenIntIndex(reg);
446}
447
448template <class Impl>
449int
450O3ThreadContext<Impl>::flattenFloatIndex(int reg)
451{
452 return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
453}
454
455template <class Impl>
442void
443O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
444{
445 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
446
447 // Squash if we're not already in a state update mode.
448 if (!thread->trapPending && !thread->inSyscall) {
449 cpu->squashFromTC(thread->threadId());

--- 16 unchanged lines hidden --- 		456void
457O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
458{
459 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
460
461 // Squash if we're not already in a state update mode.
462 if (!thread->trapPending && !thread->inSyscall) {
463 cpu->squashFromTC(thread->threadId());

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