thread_context_impl.hh (5714:76abee886def) | thread_context_impl.hh (5715:e8c1d4e669a7) |
---|---|
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59#else 60 assert(getProcessPtr() == old_context->getProcessPtr()); 61#endif 62 63 // copy over functional state 64 setStatus(old_context->status()); 65 copyArchRegs(old_context); 66 setContextId(old_context->contextId()); | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59#else 60 assert(getProcessPtr() == old_context->getProcessPtr()); 61#endif 62 63 // copy over functional state 64 setStatus(old_context->status()); 65 copyArchRegs(old_context); 66 setContextId(old_context->contextId()); |
67 setThreadId(old_context->threadId()); |
|
67 68#if !FULL_SYSTEM 69 thread->funcExeInst = old_context->readFuncExeInst(); 70#else 71 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 72 if (other_quiesce) { 73 // Point the quiesce event's TC at this TC so that it wakes up 74 // the proper CPU. --- 15 unchanged lines hidden (view full) --- 90 thread->trapPending = false; 91} 92 93template <class Impl> 94void 95O3ThreadContext<Impl>::activate(int delay) 96{ 97 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", | 68 69#if !FULL_SYSTEM 70 thread->funcExeInst = old_context->readFuncExeInst(); 71#else 72 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 73 if (other_quiesce) { 74 // Point the quiesce event's TC at this TC so that it wakes up 75 // the proper CPU. --- 15 unchanged lines hidden (view full) --- 91 thread->trapPending = false; 92} 93 94template <class Impl> 95void 96O3ThreadContext<Impl>::activate(int delay) 97{ 98 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", |
98 getThreadNum()); | 99 threadId()); |
99 100 if (thread->status() == ThreadContext::Active) 101 return; 102 103#if FULL_SYSTEM 104 thread->lastActivate = curTick; 105#endif 106 107 if (thread->status() == ThreadContext::Unallocated) { | 100 101 if (thread->status() == ThreadContext::Active) 102 return; 103 104#if FULL_SYSTEM 105 thread->lastActivate = curTick; 106#endif 107 108 if (thread->status() == ThreadContext::Unallocated) { |
108 cpu->activateWhenReady(thread->readTid()); | 109 cpu->activateWhenReady(thread->threadId()); |
109 return; 110 } 111 112 thread->setStatus(ThreadContext::Active); 113 114 // status() == Suspended | 110 return; 111 } 112 113 thread->setStatus(ThreadContext::Active); 114 115 // status() == Suspended |
115 cpu->activateContext(thread->readTid(), delay); | 116 cpu->activateContext(thread->threadId(), delay); |
116} 117 118template <class Impl> 119void 120O3ThreadContext<Impl>::suspend(int delay) 121{ 122 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", | 117} 118 119template <class Impl> 120void 121O3ThreadContext<Impl>::suspend(int delay) 122{ 123 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", |
123 getThreadNum()); | 124 threadId()); |
124 125 if (thread->status() == ThreadContext::Suspended) 126 return; 127 128#if FULL_SYSTEM 129 thread->lastActivate = curTick; 130 thread->lastSuspend = curTick; 131#endif 132/* 133#if FULL_SYSTEM 134 // Don't change the status from active if there are pending interrupts 135 if (cpu->checkInterrupts()) { 136 assert(status() == ThreadContext::Active); 137 return; 138 } 139#endif 140*/ 141 thread->setStatus(ThreadContext::Suspended); | 125 126 if (thread->status() == ThreadContext::Suspended) 127 return; 128 129#if FULL_SYSTEM 130 thread->lastActivate = curTick; 131 thread->lastSuspend = curTick; 132#endif 133/* 134#if FULL_SYSTEM 135 // Don't change the status from active if there are pending interrupts 136 if (cpu->checkInterrupts()) { 137 assert(status() == ThreadContext::Active); 138 return; 139 } 140#endif 141*/ 142 thread->setStatus(ThreadContext::Suspended); |
142 cpu->suspendContext(thread->readTid()); | 143 cpu->suspendContext(thread->threadId()); |
143} 144 145template <class Impl> 146void 147O3ThreadContext<Impl>::deallocate(int delay) 148{ 149 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", | 144} 145 146template <class Impl> 147void 148O3ThreadContext<Impl>::deallocate(int delay) 149{ 150 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", |
150 getThreadNum(), delay); | 151 threadId(), delay); |
151 152 if (thread->status() == ThreadContext::Unallocated) 153 return; 154 155 thread->setStatus(ThreadContext::Unallocated); | 152 153 if (thread->status() == ThreadContext::Unallocated) 154 return; 155 156 thread->setStatus(ThreadContext::Unallocated); |
156 cpu->deallocateContext(thread->readTid(), true, delay); | 157 cpu->deallocateContext(thread->threadId(), true, delay); |
157} 158 159template <class Impl> 160void 161O3ThreadContext<Impl>::halt(int delay) 162{ 163 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", | 158} 159 160template <class Impl> 161void 162O3ThreadContext<Impl>::halt(int delay) 163{ 164 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", |
164 getThreadNum()); | 165 threadId()); |
165 166 if (thread->status() == ThreadContext::Halted) 167 return; 168 169 thread->setStatus(ThreadContext::Halted); | 166 167 if (thread->status() == ThreadContext::Halted) 168 return; 169 170 thread->setStatus(ThreadContext::Halted); |
170 cpu->haltContext(thread->readTid()); | 171 cpu->haltContext(thread->threadId()); |
171} 172 173template <class Impl> 174void 175O3ThreadContext<Impl>::regStats(const std::string &name) 176{ 177#if FULL_SYSTEM 178 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); --- 61 unchanged lines hidden (view full) --- 240} 241 242template <class Impl> 243void 244O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 245{ 246 // This function will mess things up unless the ROB is empty and 247 // there are no instructions in the pipeline. | 172} 173 174template <class Impl> 175void 176O3ThreadContext<Impl>::regStats(const std::string &name) 177{ 178#if FULL_SYSTEM 179 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); --- 61 unchanged lines hidden (view full) --- 241} 242 243template <class Impl> 244void 245O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 246{ 247 // This function will mess things up unless the ROB is empty and 248 // there are no instructions in the pipeline. |
248 unsigned tid = thread->readTid(); | 249 unsigned tid = thread->threadId(); |
249 PhysRegIndex renamed_reg; 250 251 // First loop through the integer registers. 252 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 253 renamed_reg = cpu->renameMap[tid].lookup(i); 254 255 DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 256 "now has data %lli.\n", --- 30 unchanged lines hidden (view full) --- 287O3ThreadContext<Impl>::clearArchRegs() 288{} 289 290template <class Impl> 291uint64_t 292O3ThreadContext<Impl>::readIntReg(int reg_idx) 293{ 294 reg_idx = TheISA::flattenIntIndex(this, reg_idx); | 250 PhysRegIndex renamed_reg; 251 252 // First loop through the integer registers. 253 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 254 renamed_reg = cpu->renameMap[tid].lookup(i); 255 256 DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 257 "now has data %lli.\n", --- 30 unchanged lines hidden (view full) --- 288O3ThreadContext<Impl>::clearArchRegs() 289{} 290 291template <class Impl> 292uint64_t 293O3ThreadContext<Impl>::readIntReg(int reg_idx) 294{ 295 reg_idx = TheISA::flattenIntIndex(this, reg_idx); |
295 return cpu->readArchIntReg(reg_idx, thread->readTid()); | 296 return cpu->readArchIntReg(reg_idx, thread->threadId()); |
296} 297 298template <class Impl> 299TheISA::FloatReg 300O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 301{ 302 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 303 switch(width) { 304 case 32: | 297} 298 299template <class Impl> 300TheISA::FloatReg 301O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 302{ 303 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 304 switch(width) { 305 case 32: |
305 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); | 306 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); |
306 case 64: | 307 case 64: |
307 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); | 308 return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); |
308 default: 309 panic("Unsupported width!"); 310 return 0; 311 } 312} 313 314template <class Impl> 315TheISA::FloatReg 316O3ThreadContext<Impl>::readFloatReg(int reg_idx) 317{ 318 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 309 default: 310 panic("Unsupported width!"); 311 return 0; 312 } 313} 314 315template <class Impl> 316TheISA::FloatReg 317O3ThreadContext<Impl>::readFloatReg(int reg_idx) 318{ 319 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
319 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); | 320 return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); |
320} 321 322template <class Impl> 323TheISA::FloatRegBits 324O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 325{ 326 DPRINTF(Fault, "Reading floatint register through the TC!\n"); 327 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 321} 322 323template <class Impl> 324TheISA::FloatRegBits 325O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 326{ 327 DPRINTF(Fault, "Reading floatint register through the TC!\n"); 328 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
328 return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); | 329 return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); |
329} 330 331template <class Impl> 332TheISA::FloatRegBits 333O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 334{ 335 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 330} 331 332template <class Impl> 333TheISA::FloatRegBits 334O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 335{ 336 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
336 return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); | 337 return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); |
337} 338 339template <class Impl> 340void 341O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 342{ 343 reg_idx = TheISA::flattenIntIndex(this, reg_idx); | 338} 339 340template <class Impl> 341void 342O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 343{ 344 reg_idx = TheISA::flattenIntIndex(this, reg_idx); |
344 cpu->setArchIntReg(reg_idx, val, thread->readTid()); | 345 cpu->setArchIntReg(reg_idx, val, thread->threadId()); |
345 346 // Squash if we're not already in a state update mode. 347 if (!thread->trapPending && !thread->inSyscall) { | 346 347 // Squash if we're not already in a state update mode. 348 if (!thread->trapPending && !thread->inSyscall) { |
348 cpu->squashFromTC(thread->readTid()); | 349 cpu->squashFromTC(thread->threadId()); |
349 } 350} 351 352template <class Impl> 353void 354O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 355{ 356 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 357 switch(width) { 358 case 32: | 350 } 351} 352 353template <class Impl> 354void 355O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 356{ 357 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 358 switch(width) { 359 case 32: |
359 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); | 360 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); |
360 break; 361 case 64: | 361 break; 362 case 64: |
362 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); | 363 cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); |
363 break; 364 } 365 366 // Squash if we're not already in a state update mode. 367 if (!thread->trapPending && !thread->inSyscall) { | 364 break; 365 } 366 367 // Squash if we're not already in a state update mode. 368 if (!thread->trapPending && !thread->inSyscall) { |
368 cpu->squashFromTC(thread->readTid()); | 369 cpu->squashFromTC(thread->threadId()); |
369 } 370} 371 372template <class Impl> 373void 374O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 375{ 376 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 370 } 371} 372 373template <class Impl> 374void 375O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 376{ 377 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
377 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); | 378 cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); |
378 379 if (!thread->trapPending && !thread->inSyscall) { | 379 380 if (!thread->trapPending && !thread->inSyscall) { |
380 cpu->squashFromTC(thread->readTid()); | 381 cpu->squashFromTC(thread->threadId()); |
381 } 382} 383 384template <class Impl> 385void 386O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 387 int width) 388{ 389 DPRINTF(Fault, "Setting floatint register through the TC!\n"); 390 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 382 } 383} 384 385template <class Impl> 386void 387O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 388 int width) 389{ 390 DPRINTF(Fault, "Setting floatint register through the TC!\n"); 391 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
391 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); | 392 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); |
392 393 // Squash if we're not already in a state update mode. 394 if (!thread->trapPending && !thread->inSyscall) { | 393 394 // Squash if we're not already in a state update mode. 395 if (!thread->trapPending && !thread->inSyscall) { |
395 cpu->squashFromTC(thread->readTid()); | 396 cpu->squashFromTC(thread->threadId()); |
396 } 397} 398 399template <class Impl> 400void 401O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 402{ 403 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); | 397 } 398} 399 400template <class Impl> 401void 402O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 403{ 404 reg_idx = TheISA::flattenFloatIndex(this, reg_idx); |
404 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); | 405 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); |
405 406 // Squash if we're not already in a state update mode. 407 if (!thread->trapPending && !thread->inSyscall) { | 406 407 // Squash if we're not already in a state update mode. 408 if (!thread->trapPending && !thread->inSyscall) { |
408 cpu->squashFromTC(thread->readTid()); | 409 cpu->squashFromTC(thread->threadId()); |
409 } 410} 411 412template <class Impl> 413void 414O3ThreadContext<Impl>::setPC(uint64_t val) 415{ | 410 } 411} 412 413template <class Impl> 414void 415O3ThreadContext<Impl>::setPC(uint64_t val) 416{ |
416 cpu->setPC(val, thread->readTid()); | 417 cpu->setPC(val, thread->threadId()); |
417 418 // Squash if we're not already in a state update mode. 419 if (!thread->trapPending && !thread->inSyscall) { | 418 419 // Squash if we're not already in a state update mode. 420 if (!thread->trapPending && !thread->inSyscall) { |
420 cpu->squashFromTC(thread->readTid()); | 421 cpu->squashFromTC(thread->threadId()); |
421 } 422} 423 424template <class Impl> 425void 426O3ThreadContext<Impl>::setNextPC(uint64_t val) 427{ | 422 } 423} 424 425template <class Impl> 426void 427O3ThreadContext<Impl>::setNextPC(uint64_t val) 428{ |
428 cpu->setNextPC(val, thread->readTid()); | 429 cpu->setNextPC(val, thread->threadId()); |
429 430 // Squash if we're not already in a state update mode. 431 if (!thread->trapPending && !thread->inSyscall) { | 430 431 // Squash if we're not already in a state update mode. 432 if (!thread->trapPending && !thread->inSyscall) { |
432 cpu->squashFromTC(thread->readTid()); | 433 cpu->squashFromTC(thread->threadId()); |
433 } 434} 435 436template <class Impl> 437void 438O3ThreadContext<Impl>::setMicroPC(uint64_t val) 439{ | 434 } 435} 436 437template <class Impl> 438void 439O3ThreadContext<Impl>::setMicroPC(uint64_t val) 440{ |
440 cpu->setMicroPC(val, thread->readTid()); | 441 cpu->setMicroPC(val, thread->threadId()); |
441 442 // Squash if we're not already in a state update mode. 443 if (!thread->trapPending && !thread->inSyscall) { | 442 443 // Squash if we're not already in a state update mode. 444 if (!thread->trapPending && !thread->inSyscall) { |
444 cpu->squashFromTC(thread->readTid()); | 445 cpu->squashFromTC(thread->threadId()); |
445 } 446} 447 448template <class Impl> 449void 450O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 451{ | 446 } 447} 448 449template <class Impl> 450void 451O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 452{ |
452 cpu->setNextMicroPC(val, thread->readTid()); | 453 cpu->setNextMicroPC(val, thread->threadId()); |
453 454 // Squash if we're not already in a state update mode. 455 if (!thread->trapPending && !thread->inSyscall) { | 454 455 // Squash if we're not already in a state update mode. 456 if (!thread->trapPending && !thread->inSyscall) { |
456 cpu->squashFromTC(thread->readTid()); | 457 cpu->squashFromTC(thread->threadId()); |
457 } 458} 459 460template <class Impl> 461void 462O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 463{ | 458 } 459} 460 461template <class Impl> 462void 463O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 464{ |
464 cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); | 465 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); |
465 466 // Squash if we're not already in a state update mode. 467 if (!thread->trapPending && !thread->inSyscall) { | 466 467 // Squash if we're not already in a state update mode. 468 if (!thread->trapPending && !thread->inSyscall) { |
468 cpu->squashFromTC(thread->readTid()); | 469 cpu->squashFromTC(thread->threadId()); |
469 } 470} 471 472template <class Impl> 473void 474O3ThreadContext<Impl>::setMiscReg(int misc_reg, 475 const MiscReg &val) 476{ | 470 } 471} 472 473template <class Impl> 474void 475O3ThreadContext<Impl>::setMiscReg(int misc_reg, 476 const MiscReg &val) 477{ |
477 cpu->setMiscReg(misc_reg, val, thread->readTid()); | 478 cpu->setMiscReg(misc_reg, val, thread->threadId()); |
478 479 // Squash if we're not already in a state update mode. 480 if (!thread->trapPending && !thread->inSyscall) { | 479 480 // Squash if we're not already in a state update mode. 481 if (!thread->trapPending && !thread->inSyscall) { |
481 cpu->squashFromTC(thread->readTid()); | 482 cpu->squashFromTC(thread->threadId()); |
482 } 483} 484 485#if !FULL_SYSTEM 486 487template <class Impl> 488TheISA::IntReg 489O3ThreadContext<Impl>::getSyscallArg(int i) 490{ | 483 } 484} 485 486#if !FULL_SYSTEM 487 488template <class Impl> 489TheISA::IntReg 490O3ThreadContext<Impl>::getSyscallArg(int i) 491{ |
491 return cpu->getSyscallArg(i, thread->readTid()); | 492 return cpu->getSyscallArg(i, thread->threadId()); |
492} 493 494template <class Impl> 495void 496O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 497{ | 493} 494 495template <class Impl> 496void 497O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 498{ |
498 cpu->setSyscallArg(i, val, thread->readTid()); | 499 cpu->setSyscallArg(i, val, thread->threadId()); |
499} 500 501template <class Impl> 502void 503O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 504{ | 500} 501 502template <class Impl> 503void 504O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 505{ |
505 cpu->setSyscallReturn(return_value, thread->readTid()); | 506 cpu->setSyscallReturn(return_value, thread->threadId()); |
506} 507 508#endif // FULL_SYSTEM 509 | 507} 508 509#endif // FULL_SYSTEM 510 |