thread_context_impl.hh (13601:f5c84915eb7f) thread_context_impl.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230 const ElemIndex& elemIndex) const
231{
232 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 219 unchanged lines hidden (view full) ---

228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230 const ElemIndex& elemIndex) const
231{
232 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
236const TheISA::VecPredRegContainer&
237O3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const
238{
239 return cpu->readArchVecPredReg(reg_id, thread->threadId());
240}
241
242template <class Impl>
243TheISA::VecPredRegContainer&
244O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
245{
246 return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
247}
248
249template <class Impl>
236TheISA::CCReg
237O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
238{
239 return cpu->readArchCCReg(reg_idx, thread->threadId());
240}
241
242template <class Impl>
243void

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272 const ElemIndex& elemIndex, const VecElem& val)
273{
274 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
275 conditionalSquash();
276}
277
278template <class Impl>
279void
250TheISA::CCReg
251O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
252{
253 return cpu->readArchCCReg(reg_idx, thread->threadId());
254}
255
256template <class Impl>
257void

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286 const ElemIndex& elemIndex, const VecElem& val)
287{
288 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
289 conditionalSquash();
290}
291
292template <class Impl>
293void
294O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
295 const VecPredRegContainer& val)
296{
297 cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
298
299 conditionalSquash();
300}
301
302template <class Impl>
303void
280O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
281{
282 cpu->setArchCCReg(reg_idx, val, thread->threadId());
283
284 conditionalSquash();
285}
286
287template <class Impl>

--- 43 unchanged lines hidden --- 		304O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
305{
306 cpu->setArchCCReg(reg_idx, val, thread->threadId());
307
308 conditionalSquash();
309}
310
311template <class Impl>

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