thread_context_impl.hh (12106:7784fac1b159) thread_context_impl.hh (12109:f29e9c5418aa)
1/*
1/*
2 * Copyright (c) 2010-2012 ARM Limited
2 * Copyright (c) 2010-2012, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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204template <class Impl>
205TheISA::FloatRegBits
206O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
207{
208 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
209}
210
211template <class Impl>
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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204template <class Impl>
205TheISA::FloatRegBits
206O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
207{
208 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
209}
210
211template <class Impl>
212const TheISA::VecRegContainer&
213O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
214{
215 return cpu->readArchVecReg(reg_id, thread->threadId());
216}
217
218template <class Impl>
219TheISA::VecRegContainer&
220O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
221{
222 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
223}
224
225template <class Impl>
226const TheISA::VecElem&
227O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
228 const ElemIndex& elemIndex) const
229{
230 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
231}
232
233template <class Impl>
212TheISA::CCReg
213O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
214{
215 return cpu->readArchCCReg(reg_idx, thread->threadId());
216}
217
218template <class Impl>
219void

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239{
240 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
241
242 conditionalSquash();
243}
244
245template <class Impl>
246void
234TheISA::CCReg
235O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
236{
237 return cpu->readArchCCReg(reg_idx, thread->threadId());
238}
239
240template <class Impl>
241void

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261{
262 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
263
264 conditionalSquash();
265}
266
267template <class Impl>
268void
269O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
270{
271 cpu->setArchVecReg(reg_idx, val, thread->threadId());
272
273 conditionalSquash();
274}
275
276template <class Impl>
277void
278O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
279 const ElemIndex& elemIndex, const VecElem& val)
280{
281 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
282 conditionalSquash();
283}
284
285template <class Impl>
286void
247O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
248{
249 cpu->setArchCCReg(reg_idx, val, thread->threadId());
250
251 conditionalSquash();
252}
253
254template <class Impl>

--- 43 unchanged lines hidden --- 		287O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
288{
289 cpu->setArchCCReg(reg_idx, val, thread->threadId());
290
291 conditionalSquash();
292}
293
294template <class Impl>

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