thread_context_impl.hh (10935:acd48ddd725f) thread_context_impl.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 256 unchanged lines hidden (view full) ---

265O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
266{
267 cpu->pcState(val, thread->threadId());
268
269 conditionalSquash();
270}
271
272template <class Impl>
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 256 unchanged lines hidden (view full) ---

265O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
266{
267 cpu->pcState(val, thread->threadId());
268
269 conditionalSquash();
270}
271
272template <class Impl>
273int
274O3ThreadContext<Impl>::flattenIntIndex(int reg)
273RegId
274O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
275{
275{
276 return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
276 return cpu->isa[thread->threadId()]->flattenRegId(regId);
277}
278
279template <class Impl>
277}
278
279template <class Impl>
280int
281O3ThreadContext<Impl>::flattenFloatIndex(int reg)
282{
283 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
284}
285
286template <class Impl>
287int
288O3ThreadContext<Impl>::flattenCCIndex(int reg)
289{
290 return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
291}
292
293template <class Impl>
294int
295O3ThreadContext<Impl>::flattenMiscIndex(int reg)
296{
297 return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
303{
304 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
305
306 conditionalSquash();
307}
308
309#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
310template <class Impl>
311void
312O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
313{
314 cpu->setMiscReg(misc_reg, val, thread->threadId());
315
316 conditionalSquash();
317}
318
280void
281O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
282{
283 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
284
285 conditionalSquash();
286}
287
288#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
289template <class Impl>
290void
291O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
292{
293 cpu->setMiscReg(misc_reg, val, thread->threadId());
294
295 conditionalSquash();
296}
297