thread_context_impl.hh (10934:5af8f40d8f2c) thread_context_impl.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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211template <class Impl>
212TheISA::CCReg
213O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
214{
215 return cpu->readArchCCReg(reg_idx, thread->threadId());
216}
217
218template <class Impl>
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 202 unchanged lines hidden (view full) ---

211template <class Impl>
212TheISA::CCReg
213O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
214{
215 return cpu->readArchCCReg(reg_idx, thread->threadId());
216}
217
218template <class Impl>
219const TheISA::VectorReg &
220O3ThreadContext<Impl>::readVectorRegFlat(int reg_idx)
221{
222 return cpu->readArchVectorReg(reg_idx, thread->threadId());
223}
224
225template <class Impl>
226void
227O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
228{
229 cpu->setArchIntReg(reg_idx, val, thread->threadId());
230
231 conditionalSquash();
232}
233

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255{
256 cpu->setArchCCReg(reg_idx, val, thread->threadId());
257
258 conditionalSquash();
259}
260
261template <class Impl>
262void
219void
220O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
221{
222 cpu->setArchIntReg(reg_idx, val, thread->threadId());
223
224 conditionalSquash();
225}
226

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248{
249 cpu->setArchCCReg(reg_idx, val, thread->threadId());
250
251 conditionalSquash();
252}
253
254template <class Impl>
255void
263O3ThreadContext<Impl>::setVectorRegFlat(int reg_idx,
264 const TheISA::VectorReg &val)
265{
266 cpu->setArchVectorReg(reg_idx, val, thread->threadId());
267 conditionalSquash();
268}
269
270template <class Impl>
271void
272O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
273{
274 cpu->pcState(val, thread->threadId());
275
276 conditionalSquash();
277}
278
279template <class Impl>

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303int
304O3ThreadContext<Impl>::flattenCCIndex(int reg)
305{
306 return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
307}
308
309template <class Impl>
310int
256O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
257{
258 cpu->pcState(val, thread->threadId());
259
260 conditionalSquash();
261}
262
263template <class Impl>

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287int
288O3ThreadContext<Impl>::flattenCCIndex(int reg)
289{
290 return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
291}
292
293template <class Impl>
294int
311O3ThreadContext<Impl>::flattenVectorIndex(int reg)
312{
313 return cpu->isa[thread->threadId()]->flattenVectorIndex(reg);
314}
315
316template <class Impl>
317int
318O3ThreadContext<Impl>::flattenMiscIndex(int reg)
319{
320 return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
321}
322
323template <class Impl>
324void
325O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

--- 16 unchanged lines hidden --- 		295O3ThreadContext<Impl>::flattenMiscIndex(int reg)
296{
297 return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
298}
299
300template <class Impl>
301void
302O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

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