1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 256 unchanged lines hidden (view full) --- 265O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 266{ 267 cpu->pcState(val, thread->threadId()); 268 269 conditionalSquash(); 270} 271 272template <class Impl> |
273RegId 274O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const |
275{ |
276 return cpu->isa[thread->threadId()]->flattenRegId(regId); |
277} 278 279template <class Impl> |
280void 281O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 282{ 283 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 284 285 conditionalSquash(); 286} 287 288#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 289template <class Impl> 290void 291O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 292{ 293 cpu->setMiscReg(misc_reg, val, thread->threadId()); 294 295 conditionalSquash(); 296} 297 |