1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 202 unchanged lines hidden (view full) --- 211template <class Impl> 212TheISA::CCReg 213O3ThreadContext<Impl>::readCCRegFlat(int reg_idx) 214{ 215 return cpu->readArchCCReg(reg_idx, thread->threadId()); 216} 217 218template <class Impl> |
219void 220O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) 221{ 222 cpu->setArchIntReg(reg_idx, val, thread->threadId()); 223 224 conditionalSquash(); 225} 226 --- 21 unchanged lines hidden (view full) --- 248{ 249 cpu->setArchCCReg(reg_idx, val, thread->threadId()); 250 251 conditionalSquash(); 252} 253 254template <class Impl> 255void |
256O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 257{ 258 cpu->pcState(val, thread->threadId()); 259 260 conditionalSquash(); 261} 262 263template <class Impl> --- 23 unchanged lines hidden (view full) --- 287int 288O3ThreadContext<Impl>::flattenCCIndex(int reg) 289{ 290 return cpu->isa[thread->threadId()]->flattenCCIndex(reg); 291} 292 293template <class Impl> 294int |
295O3ThreadContext<Impl>::flattenMiscIndex(int reg) 296{ 297 return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); 298} 299 300template <class Impl> 301void 302O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) --- 16 unchanged lines hidden --- |