2c2
< * Copyright (c) 2010-2012 ARM Limited
---
> * Copyright (c) 2010-2012, 2016 ARM Limited
211a212,233
> const TheISA::VecRegContainer&
> O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
> {
> return cpu->readArchVecReg(reg_id, thread->threadId());
> }
>
> template <class Impl>
> TheISA::VecRegContainer&
> O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
> {
> return cpu->getWritableArchVecReg(reg_id, thread->threadId());
> }
>
> template <class Impl>
> const TheISA::VecElem&
> O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
> const ElemIndex& elemIndex) const
> {
> return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
> }
>
> template <class Impl>
246a269,286
> O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
> {
> cpu->setArchVecReg(reg_idx, val, thread->threadId());
>
> conditionalSquash();
> }
>
> template <class Impl>
> void
> O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
> const ElemIndex& elemIndex, const VecElem& val)
> {
> cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
> conditionalSquash();
> }
>
> template <class Impl>
> void