1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "cpu/o3/thread_context.hh"
48#include "cpu/quiesce_event.hh"
49#include "debug/O3CPU.hh"
50
51template <class Impl>
52FSTranslatingPortProxy&
53O3ThreadContext<Impl>::getVirtProxy()
54{
55 return thread->getVirtProxy();
56}
57
58template <class Impl>
59void
60O3ThreadContext<Impl>::dumpFuncProfile()
61{
62 thread->dumpFuncProfile();
63}
64
65template <class Impl>
66void
67O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
68{
69 ::takeOverFrom(*this, *old_context);
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "cpu/o3/thread_context.hh"
48#include "cpu/quiesce_event.hh"
49#include "debug/O3CPU.hh"
50
51template <class Impl>
52FSTranslatingPortProxy&
53O3ThreadContext<Impl>::getVirtProxy()
54{
55 return thread->getVirtProxy();
56}
57
58template <class Impl>
59void
60O3ThreadContext<Impl>::dumpFuncProfile()
61{
62 thread->dumpFuncProfile();
63}
64
65template <class Impl>
66void
67O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
68{
69 ::takeOverFrom(*this, *old_context);
|
70
71 thread->kernelStats = old_context->getKernelStats();
72 thread->funcExeInst = old_context->readFuncExeInst();
73
74 thread->noSquashFromTC = false;
75 thread->trapPending = false;
76}
77
78template <class Impl>
79void
80O3ThreadContext<Impl>::activate(Cycles delay)
81{
82 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
83 threadId());
84
85 if (thread->status() == ThreadContext::Active)
86 return;
87
88 thread->lastActivate = curTick();
89 thread->setStatus(ThreadContext::Active);
90
91 // status() == Suspended
92 cpu->activateContext(thread->threadId(), delay);
93}
94
95template <class Impl>
96void
97O3ThreadContext<Impl>::suspend(Cycles delay)
98{
99 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
100 threadId());
101
102 if (thread->status() == ThreadContext::Suspended)
103 return;
104
105 thread->lastActivate = curTick();
106 thread->lastSuspend = curTick();
107
108 thread->setStatus(ThreadContext::Suspended);
109 cpu->suspendContext(thread->threadId());
110}
111
112template <class Impl>
113void
114O3ThreadContext<Impl>::halt(Cycles delay)
115{
116 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
117 threadId());
118
119 if (thread->status() == ThreadContext::Halted)
120 return;
121
122 thread->setStatus(ThreadContext::Halted);
123 cpu->haltContext(thread->threadId());
124}
125
126template <class Impl>
127void
128O3ThreadContext<Impl>::regStats(const std::string &name)
129{
130 if (FullSystem) {
131 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
132 thread->kernelStats->regStats(name + ".kern");
133 }
134}
135
136template <class Impl>
137Tick
138O3ThreadContext<Impl>::readLastActivate()
139{
140 return thread->lastActivate;
141}
142
143template <class Impl>
144Tick
145O3ThreadContext<Impl>::readLastSuspend()
146{
147 return thread->lastSuspend;
148}
149
150template <class Impl>
151void
152O3ThreadContext<Impl>::profileClear()
153{
154 thread->profileClear();
155}
156
157template <class Impl>
158void
159O3ThreadContext<Impl>::profileSample()
160{
161 thread->profileSample();
162}
163
164template <class Impl>
165void
166O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
167{
168 // Prevent squashing
169 thread->noSquashFromTC = true;
170 TheISA::copyRegs(tc, this);
171 thread->noSquashFromTC = false;
172
173 if (!FullSystem)
174 this->thread->funcExeInst = tc->readFuncExeInst();
175}
176
177template <class Impl>
178void
179O3ThreadContext<Impl>::clearArchRegs()
180{
181 cpu->isa[thread->threadId()]->clear();
182}
183
184template <class Impl>
185uint64_t
186O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
187{
188 return cpu->readArchIntReg(reg_idx, thread->threadId());
189}
190
191template <class Impl>
192TheISA::FloatReg
193O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
194{
195 return cpu->readArchFloatReg(reg_idx, thread->threadId());
196}
197
198template <class Impl>
199TheISA::FloatRegBits
200O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
201{
202 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
203}
204
205template <class Impl>
206void
207O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
208{
209 cpu->setArchIntReg(reg_idx, val, thread->threadId());
210
211 conditionalSquash();
212}
213
214template <class Impl>
215void
216O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
217{
218 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
219
220 conditionalSquash();
221}
222
223template <class Impl>
224void
225O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
226{
227 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
228
229 conditionalSquash();
230}
231
232template <class Impl>
233void
234O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
235{
236 cpu->pcState(val, thread->threadId());
237
238 conditionalSquash();
239}
240
241template <class Impl>
242void
243O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
244{
245 cpu->pcState(val, thread->threadId());
246
247 conditionalSquash();
248}
249
250template <class Impl>
251int
252O3ThreadContext<Impl>::flattenIntIndex(int reg)
253{
254 return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
255}
256
257template <class Impl>
258int
259O3ThreadContext<Impl>::flattenFloatIndex(int reg)
260{
261 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
262}
263
264template <class Impl>
265void
266O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
267{
268 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
269
270 conditionalSquash();
271}
272
273template <class Impl>
274void
275O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
276{
277 cpu->setMiscReg(misc_reg, val, thread->threadId());
278
279 conditionalSquash();
280}
281
| 73
74 thread->kernelStats = old_context->getKernelStats();
75 thread->funcExeInst = old_context->readFuncExeInst();
76
77 thread->noSquashFromTC = false;
78 thread->trapPending = false;
79}
80
81template <class Impl>
82void
83O3ThreadContext<Impl>::activate(Cycles delay)
84{
85 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
86 threadId());
87
88 if (thread->status() == ThreadContext::Active)
89 return;
90
91 thread->lastActivate = curTick();
92 thread->setStatus(ThreadContext::Active);
93
94 // status() == Suspended
95 cpu->activateContext(thread->threadId(), delay);
96}
97
98template <class Impl>
99void
100O3ThreadContext<Impl>::suspend(Cycles delay)
101{
102 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
103 threadId());
104
105 if (thread->status() == ThreadContext::Suspended)
106 return;
107
108 thread->lastActivate = curTick();
109 thread->lastSuspend = curTick();
110
111 thread->setStatus(ThreadContext::Suspended);
112 cpu->suspendContext(thread->threadId());
113}
114
115template <class Impl>
116void
117O3ThreadContext<Impl>::halt(Cycles delay)
118{
119 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
120 threadId());
121
122 if (thread->status() == ThreadContext::Halted)
123 return;
124
125 thread->setStatus(ThreadContext::Halted);
126 cpu->haltContext(thread->threadId());
127}
128
129template <class Impl>
130void
131O3ThreadContext<Impl>::regStats(const std::string &name)
132{
133 if (FullSystem) {
134 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
135 thread->kernelStats->regStats(name + ".kern");
136 }
137}
138
139template <class Impl>
140Tick
141O3ThreadContext<Impl>::readLastActivate()
142{
143 return thread->lastActivate;
144}
145
146template <class Impl>
147Tick
148O3ThreadContext<Impl>::readLastSuspend()
149{
150 return thread->lastSuspend;
151}
152
153template <class Impl>
154void
155O3ThreadContext<Impl>::profileClear()
156{
157 thread->profileClear();
158}
159
160template <class Impl>
161void
162O3ThreadContext<Impl>::profileSample()
163{
164 thread->profileSample();
165}
166
167template <class Impl>
168void
169O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
170{
171 // Prevent squashing
172 thread->noSquashFromTC = true;
173 TheISA::copyRegs(tc, this);
174 thread->noSquashFromTC = false;
175
176 if (!FullSystem)
177 this->thread->funcExeInst = tc->readFuncExeInst();
178}
179
180template <class Impl>
181void
182O3ThreadContext<Impl>::clearArchRegs()
183{
184 cpu->isa[thread->threadId()]->clear();
185}
186
187template <class Impl>
188uint64_t
189O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
190{
191 return cpu->readArchIntReg(reg_idx, thread->threadId());
192}
193
194template <class Impl>
195TheISA::FloatReg
196O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
197{
198 return cpu->readArchFloatReg(reg_idx, thread->threadId());
199}
200
201template <class Impl>
202TheISA::FloatRegBits
203O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
204{
205 return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
206}
207
208template <class Impl>
209void
210O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
211{
212 cpu->setArchIntReg(reg_idx, val, thread->threadId());
213
214 conditionalSquash();
215}
216
217template <class Impl>
218void
219O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
220{
221 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
222
223 conditionalSquash();
224}
225
226template <class Impl>
227void
228O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
229{
230 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
231
232 conditionalSquash();
233}
234
235template <class Impl>
236void
237O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
238{
239 cpu->pcState(val, thread->threadId());
240
241 conditionalSquash();
242}
243
244template <class Impl>
245void
246O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
247{
248 cpu->pcState(val, thread->threadId());
249
250 conditionalSquash();
251}
252
253template <class Impl>
254int
255O3ThreadContext<Impl>::flattenIntIndex(int reg)
256{
257 return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
258}
259
260template <class Impl>
261int
262O3ThreadContext<Impl>::flattenFloatIndex(int reg)
263{
264 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
265}
266
267template <class Impl>
268void
269O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
270{
271 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
272
273 conditionalSquash();
274}
275
276template <class Impl>
277void
278O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
279{
280 cpu->setMiscReg(misc_reg, val, thread->threadId());
281
282 conditionalSquash();
283}
284
|