1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/generic/traits.hh"
49#include "arch/kernel_stats.hh"
50#include "arch/registers.hh"
51#include "config/the_isa.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/quiesce_event.hh"
54#include "debug/O3CPU.hh"
55
56template <class Impl>
57FSTranslatingPortProxy&
58O3ThreadContext<Impl>::getVirtProxy()
59{
60 return thread->getVirtProxy();
61}
62
63template <class Impl>
64void
65O3ThreadContext<Impl>::dumpFuncProfile()
66{
67 thread->dumpFuncProfile();
68}
69
70template <class Impl>
71void
72O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
73{
74 ::takeOverFrom(*this, *old_context);
75 TheISA::Decoder *newDecoder = getDecoderPtr();
76 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
77 newDecoder->takeOverFrom(oldDecoder);
78
79 thread->kernelStats = old_context->getKernelStats();
80 thread->funcExeInst = old_context->readFuncExeInst();
81
82 thread->noSquashFromTC = false;
83 thread->trapPending = false;
84}
85
86template <class Impl>
87void
88O3ThreadContext<Impl>::activate()
89{
90 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
91 threadId());
92
93 if (thread->status() == ThreadContext::Active)
94 return;
95
96 thread->lastActivate = curTick();
97 thread->setStatus(ThreadContext::Active);
98
99 // status() == Suspended
100 cpu->activateContext(thread->threadId());
101}
102
103template <class Impl>
104void
105O3ThreadContext<Impl>::suspend()
106{
107 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
108 threadId());
109
110 if (thread->status() == ThreadContext::Suspended)
111 return;
112
113 if (cpu->isDraining()) {
114 DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
115 return;
116 }
117
118 thread->lastActivate = curTick();
119 thread->lastSuspend = curTick();
120
121 thread->setStatus(ThreadContext::Suspended);
122 cpu->suspendContext(thread->threadId());
123}
124
125template <class Impl>
126void
127O3ThreadContext<Impl>::halt()
128{
129 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
130
131 if (thread->status() == ThreadContext::Halted)
132 return;
133
134 thread->setStatus(ThreadContext::Halted);
135 cpu->haltContext(thread->threadId());
136}
137
138template <class Impl>
139void
140O3ThreadContext<Impl>::regStats(const std::string &name)
141{
142 if (FullSystem) {
143 thread->kernelStats = new TheISA::Kernel::Statistics();
144 thread->kernelStats->regStats(name + ".kern");
145 }
146}
147
148template <class Impl>
149Tick
150O3ThreadContext<Impl>::readLastActivate()
151{
152 return thread->lastActivate;
153}
154
155template <class Impl>
156Tick
157O3ThreadContext<Impl>::readLastSuspend()
158{
159 return thread->lastSuspend;
160}
161
162template <class Impl>
163void
164O3ThreadContext<Impl>::profileClear()
165{
166 thread->profileClear();
167}
168
169template <class Impl>
170void
171O3ThreadContext<Impl>::profileSample()
172{
173 thread->profileSample();
174}
175
176template <class Impl>
177void
178O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
179{
180 // Set vector renaming mode before copying registers
181 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
182
183 // Prevent squashing
184 thread->noSquashFromTC = true;
185 TheISA::copyRegs(tc, this);
186 thread->noSquashFromTC = false;
187
188 if (!FullSystem)
189 this->thread->funcExeInst = tc->readFuncExeInst();
190}
191
192template <class Impl>
193void
194O3ThreadContext<Impl>::clearArchRegs()
195{
196 cpu->isa[thread->threadId()]->clear();
197}
198
199template <class Impl>
200RegVal
201O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
202{
203 return cpu->readArchIntReg(reg_idx, thread->threadId());
204}
205
206template <class Impl>
207RegVal
208O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
209{
210 return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
211}
212
213template <class Impl>
214const TheISA::VecRegContainer&
215O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
216{
217 return cpu->readArchVecReg(reg_id, thread->threadId());
218}
219
220template <class Impl>
221TheISA::VecRegContainer&
222O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
223{
224 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
225}
226
227template <class Impl>
228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230 const ElemIndex& elemIndex) const
231{
232 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
| 1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/generic/traits.hh"
49#include "arch/kernel_stats.hh"
50#include "arch/registers.hh"
51#include "config/the_isa.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/quiesce_event.hh"
54#include "debug/O3CPU.hh"
55
56template <class Impl>
57FSTranslatingPortProxy&
58O3ThreadContext<Impl>::getVirtProxy()
59{
60 return thread->getVirtProxy();
61}
62
63template <class Impl>
64void
65O3ThreadContext<Impl>::dumpFuncProfile()
66{
67 thread->dumpFuncProfile();
68}
69
70template <class Impl>
71void
72O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
73{
74 ::takeOverFrom(*this, *old_context);
75 TheISA::Decoder *newDecoder = getDecoderPtr();
76 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
77 newDecoder->takeOverFrom(oldDecoder);
78
79 thread->kernelStats = old_context->getKernelStats();
80 thread->funcExeInst = old_context->readFuncExeInst();
81
82 thread->noSquashFromTC = false;
83 thread->trapPending = false;
84}
85
86template <class Impl>
87void
88O3ThreadContext<Impl>::activate()
89{
90 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
91 threadId());
92
93 if (thread->status() == ThreadContext::Active)
94 return;
95
96 thread->lastActivate = curTick();
97 thread->setStatus(ThreadContext::Active);
98
99 // status() == Suspended
100 cpu->activateContext(thread->threadId());
101}
102
103template <class Impl>
104void
105O3ThreadContext<Impl>::suspend()
106{
107 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
108 threadId());
109
110 if (thread->status() == ThreadContext::Suspended)
111 return;
112
113 if (cpu->isDraining()) {
114 DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
115 return;
116 }
117
118 thread->lastActivate = curTick();
119 thread->lastSuspend = curTick();
120
121 thread->setStatus(ThreadContext::Suspended);
122 cpu->suspendContext(thread->threadId());
123}
124
125template <class Impl>
126void
127O3ThreadContext<Impl>::halt()
128{
129 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
130
131 if (thread->status() == ThreadContext::Halted)
132 return;
133
134 thread->setStatus(ThreadContext::Halted);
135 cpu->haltContext(thread->threadId());
136}
137
138template <class Impl>
139void
140O3ThreadContext<Impl>::regStats(const std::string &name)
141{
142 if (FullSystem) {
143 thread->kernelStats = new TheISA::Kernel::Statistics();
144 thread->kernelStats->regStats(name + ".kern");
145 }
146}
147
148template <class Impl>
149Tick
150O3ThreadContext<Impl>::readLastActivate()
151{
152 return thread->lastActivate;
153}
154
155template <class Impl>
156Tick
157O3ThreadContext<Impl>::readLastSuspend()
158{
159 return thread->lastSuspend;
160}
161
162template <class Impl>
163void
164O3ThreadContext<Impl>::profileClear()
165{
166 thread->profileClear();
167}
168
169template <class Impl>
170void
171O3ThreadContext<Impl>::profileSample()
172{
173 thread->profileSample();
174}
175
176template <class Impl>
177void
178O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
179{
180 // Set vector renaming mode before copying registers
181 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
182
183 // Prevent squashing
184 thread->noSquashFromTC = true;
185 TheISA::copyRegs(tc, this);
186 thread->noSquashFromTC = false;
187
188 if (!FullSystem)
189 this->thread->funcExeInst = tc->readFuncExeInst();
190}
191
192template <class Impl>
193void
194O3ThreadContext<Impl>::clearArchRegs()
195{
196 cpu->isa[thread->threadId()]->clear();
197}
198
199template <class Impl>
200RegVal
201O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
202{
203 return cpu->readArchIntReg(reg_idx, thread->threadId());
204}
205
206template <class Impl>
207RegVal
208O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
209{
210 return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
211}
212
213template <class Impl>
214const TheISA::VecRegContainer&
215O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
216{
217 return cpu->readArchVecReg(reg_id, thread->threadId());
218}
219
220template <class Impl>
221TheISA::VecRegContainer&
222O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
223{
224 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
225}
226
227template <class Impl>
228const TheISA::VecElem&
229O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
230 const ElemIndex& elemIndex) const
231{
232 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
233}
234
235template <class Impl>
|
236TheISA::CCReg
237O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
238{
239 return cpu->readArchCCReg(reg_idx, thread->threadId());
240}
241
242template <class Impl>
243void
244O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
245{
246 cpu->setArchIntReg(reg_idx, val, thread->threadId());
247
248 conditionalSquash();
249}
250
251template <class Impl>
252void
253O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
254{
255 cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
256
257 conditionalSquash();
258}
259
260template <class Impl>
261void
262O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
263{
264 cpu->setArchVecReg(reg_idx, val, thread->threadId());
265
266 conditionalSquash();
267}
268
269template <class Impl>
270void
271O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
272 const ElemIndex& elemIndex, const VecElem& val)
273{
274 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
275 conditionalSquash();
276}
277
278template <class Impl>
279void
| 250TheISA::CCReg
251O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
252{
253 return cpu->readArchCCReg(reg_idx, thread->threadId());
254}
255
256template <class Impl>
257void
258O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
259{
260 cpu->setArchIntReg(reg_idx, val, thread->threadId());
261
262 conditionalSquash();
263}
264
265template <class Impl>
266void
267O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, RegVal val)
268{
269 cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
270
271 conditionalSquash();
272}
273
274template <class Impl>
275void
276O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
277{
278 cpu->setArchVecReg(reg_idx, val, thread->threadId());
279
280 conditionalSquash();
281}
282
283template <class Impl>
284void
285O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
286 const ElemIndex& elemIndex, const VecElem& val)
287{
288 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
289 conditionalSquash();
290}
291
292template <class Impl>
293void
|
280O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
281{
282 cpu->setArchCCReg(reg_idx, val, thread->threadId());
283
284 conditionalSquash();
285}
286
287template <class Impl>
288void
289O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
290{
291 cpu->pcState(val, thread->threadId());
292
293 conditionalSquash();
294}
295
296template <class Impl>
297void
298O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
299{
300 cpu->pcState(val, thread->threadId());
301
302 conditionalSquash();
303}
304
305template <class Impl>
306RegId
307O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
308{
309 return cpu->isa[thread->threadId()]->flattenRegId(regId);
310}
311
312template <class Impl>
313void
314O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
315{
316 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
317
318 conditionalSquash();
319}
320
321#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
322template <class Impl>
323void
324O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
325{
326 cpu->setMiscReg(misc_reg, val, thread->threadId());
327
328 conditionalSquash();
329}
330
| 304O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
305{
306 cpu->setArchCCReg(reg_idx, val, thread->threadId());
307
308 conditionalSquash();
309}
310
311template <class Impl>
312void
313O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
314{
315 cpu->pcState(val, thread->threadId());
316
317 conditionalSquash();
318}
319
320template <class Impl>
321void
322O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
323{
324 cpu->pcState(val, thread->threadId());
325
326 conditionalSquash();
327}
328
329template <class Impl>
330RegId
331O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
332{
333 return cpu->isa[thread->threadId()]->flattenRegId(regId);
334}
335
336template <class Impl>
337void
338O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
339{
340 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
341
342 conditionalSquash();
343}
344
345#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
346template <class Impl>
347void
348O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
349{
350 cpu->setMiscReg(misc_reg, val, thread->threadId());
351
352 conditionalSquash();
353}
354
|